1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "qbman_private.h"
8*4882a593Smuzhiyun #include <fsl-mc/fsl_qbman_portal.h>
9*4882a593Smuzhiyun #include <fsl-mc/fsl_dpaa_fd.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* All QBMan command and result structures use this "valid bit" encoding */
12*4882a593Smuzhiyun #define QB_VALID_BIT ((uint32_t)0x80)
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* Management command result codes */
15*4882a593Smuzhiyun #define QBMAN_MC_RSLT_OK 0xf0
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define QBMAN_VER_4_0_DQRR_SIZE 4
18*4882a593Smuzhiyun #define QBMAN_VER_4_1_DQRR_SIZE 8
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* --------------------- */
22*4882a593Smuzhiyun /* portal data structure */
23*4882a593Smuzhiyun /* --------------------- */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct qbman_swp {
26*4882a593Smuzhiyun const struct qbman_swp_desc *desc;
27*4882a593Smuzhiyun /* The qbman_sys (ie. arch/OS-specific) support code can put anything it
28*4882a593Smuzhiyun * needs in here. */
29*4882a593Smuzhiyun struct qbman_swp_sys sys;
30*4882a593Smuzhiyun /* Management commands */
31*4882a593Smuzhiyun struct {
32*4882a593Smuzhiyun #ifdef QBMAN_CHECKING
33*4882a593Smuzhiyun enum swp_mc_check {
34*4882a593Smuzhiyun swp_mc_can_start, /* call __qbman_swp_mc_start() */
35*4882a593Smuzhiyun swp_mc_can_submit, /* call __qbman_swp_mc_submit() */
36*4882a593Smuzhiyun swp_mc_can_poll, /* call __qbman_swp_mc_result() */
37*4882a593Smuzhiyun } check;
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun uint32_t valid_bit; /* 0x00 or 0x80 */
40*4882a593Smuzhiyun } mc;
41*4882a593Smuzhiyun /* Push dequeues */
42*4882a593Smuzhiyun uint32_t sdq;
43*4882a593Smuzhiyun /* Volatile dequeues */
44*4882a593Smuzhiyun struct {
45*4882a593Smuzhiyun /* VDQCR supports a "1 deep pipeline", meaning that if you know
46*4882a593Smuzhiyun * the last-submitted command is already executing in the
47*4882a593Smuzhiyun * hardware (as evidenced by at least 1 valid dequeue result),
48*4882a593Smuzhiyun * you can write another dequeue command to the register, the
49*4882a593Smuzhiyun * hardware will start executing it as soon as the
50*4882a593Smuzhiyun * already-executing command terminates. (This minimises latency
51*4882a593Smuzhiyun * and stalls.) With that in mind, this "busy" variable refers
52*4882a593Smuzhiyun * to whether or not a command can be submitted, not whether or
53*4882a593Smuzhiyun * not a previously-submitted command is still executing. In
54*4882a593Smuzhiyun * other words, once proof is seen that the previously-submitted
55*4882a593Smuzhiyun * command is executing, "vdq" is no longer "busy".
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun atomic_t busy;
58*4882a593Smuzhiyun uint32_t valid_bit; /* 0x00 or 0x80 */
59*4882a593Smuzhiyun /* We need to determine when vdq is no longer busy. This depends
60*4882a593Smuzhiyun * on whether the "busy" (last-submitted) dequeue command is
61*4882a593Smuzhiyun * targeting DQRR or main-memory, and detected is based on the
62*4882a593Smuzhiyun * presence of the dequeue command's "token" showing up in
63*4882a593Smuzhiyun * dequeue entries in DQRR or main-memory (respectively). Debug
64*4882a593Smuzhiyun * builds will, when submitting vdq commands, verify that the
65*4882a593Smuzhiyun * dequeue result location is not already equal to the command's
66*4882a593Smuzhiyun * token value. */
67*4882a593Smuzhiyun struct ldpaa_dq *storage; /* NULL if DQRR */
68*4882a593Smuzhiyun uint32_t token;
69*4882a593Smuzhiyun } vdq;
70*4882a593Smuzhiyun /* DQRR */
71*4882a593Smuzhiyun struct {
72*4882a593Smuzhiyun uint32_t next_idx;
73*4882a593Smuzhiyun uint32_t valid_bit;
74*4882a593Smuzhiyun uint8_t dqrr_size;
75*4882a593Smuzhiyun } dqrr;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* -------------------------- */
79*4882a593Smuzhiyun /* portal management commands */
80*4882a593Smuzhiyun /* -------------------------- */
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Different management commands all use this common base layer of code to issue
83*4882a593Smuzhiyun * commands and poll for results. The first function returns a pointer to where
84*4882a593Smuzhiyun * the caller should fill in their MC command (though they should ignore the
85*4882a593Smuzhiyun * verb byte), the second function commits merges in the caller-supplied command
86*4882a593Smuzhiyun * verb (which should not include the valid-bit) and submits the command to
87*4882a593Smuzhiyun * hardware, and the third function checks for a completed response (returns
88*4882a593Smuzhiyun * non-NULL if only if the response is complete). */
89*4882a593Smuzhiyun void *qbman_swp_mc_start(struct qbman_swp *p);
90*4882a593Smuzhiyun void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb);
91*4882a593Smuzhiyun void *qbman_swp_mc_result(struct qbman_swp *p);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Wraps up submit + poll-for-result */
qbman_swp_mc_complete(struct qbman_swp * swp,void * cmd,uint32_t cmd_verb)94*4882a593Smuzhiyun static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
95*4882a593Smuzhiyun uint32_t cmd_verb)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun int loopvar;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun qbman_swp_mc_submit(swp, cmd, cmd_verb);
100*4882a593Smuzhiyun DBG_POLL_START(loopvar);
101*4882a593Smuzhiyun do {
102*4882a593Smuzhiyun DBG_POLL_CHECK(loopvar);
103*4882a593Smuzhiyun cmd = qbman_swp_mc_result(swp);
104*4882a593Smuzhiyun } while (!cmd);
105*4882a593Smuzhiyun return cmd;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* ------------ */
109*4882a593Smuzhiyun /* qb_attr_code */
110*4882a593Smuzhiyun /* ------------ */
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
113*4882a593Smuzhiyun * is either serving as a configuration command or a query result. The
114*4882a593Smuzhiyun * representation is inherently little-endian, as the indexing of the words is
115*4882a593Smuzhiyun * itself little-endian in nature and layerscape is little endian for anything
116*4882a593Smuzhiyun * that crosses a word boundary too (64-bit fields are the obvious examples).
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun struct qb_attr_code {
119*4882a593Smuzhiyun unsigned int word; /* which uint32_t[] array member encodes the field */
120*4882a593Smuzhiyun unsigned int lsoffset; /* encoding offset from ls-bit */
121*4882a593Smuzhiyun unsigned int width; /* encoding width. (bool must be 1.) */
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Macros to define codes */
125*4882a593Smuzhiyun #define QB_CODE(a, b, c) { a, b, c}
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* decode a field from a cacheline */
qb_attr_code_decode(const struct qb_attr_code * code,const uint32_t * cacheline)128*4882a593Smuzhiyun static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
129*4882a593Smuzhiyun const uint32_t *cacheline)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* encode a field to a cacheline */
qb_attr_code_encode(const struct qb_attr_code * code,uint32_t * cacheline,uint32_t val)136*4882a593Smuzhiyun static inline void qb_attr_code_encode(const struct qb_attr_code *code,
137*4882a593Smuzhiyun uint32_t *cacheline, uint32_t val)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun cacheline[code->word] =
140*4882a593Smuzhiyun r32_uint32_t(code->lsoffset, code->width, cacheline[code->word])
141*4882a593Smuzhiyun | e32_uint32_t(code->lsoffset, code->width, val);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
qb_attr_code_encode_64(const struct qb_attr_code * code,uint64_t * cacheline,uint64_t val)144*4882a593Smuzhiyun static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
145*4882a593Smuzhiyun uint64_t *cacheline, uint64_t val)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun cacheline[code->word / 2] = val;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* ---------------------- */
151*4882a593Smuzhiyun /* Descriptors/cachelines */
152*4882a593Smuzhiyun /* ---------------------- */
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* To avoid needless dynamic allocation, the driver API often gives the caller
155*4882a593Smuzhiyun * a "descriptor" type that the caller can instantiate however they like.
156*4882a593Smuzhiyun * Ultimately though, it is just a cacheline of binary storage (or something
157*4882a593Smuzhiyun * smaller when it is known that the descriptor doesn't need all 64 bytes) for
158*4882a593Smuzhiyun * holding pre-formatted pieces of hardware commands. The performance-critical
159*4882a593Smuzhiyun * code can then copy these descriptors directly into hardware command
160*4882a593Smuzhiyun * registers more efficiently than trying to construct/format commands
161*4882a593Smuzhiyun * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
162*4882a593Smuzhiyun * order for the compiler to know its size, but the internal details are not
163*4882a593Smuzhiyun * exposed. The following macro is used within the driver for converting *any*
164*4882a593Smuzhiyun * descriptor pointer to a usable array pointer. The use of a macro (instead of
165*4882a593Smuzhiyun * an inline) is necessary to work with different descriptor types and to work
166*4882a593Smuzhiyun * correctly with const and non-const inputs (and similarly-qualified outputs).
167*4882a593Smuzhiyun */
168*4882a593Smuzhiyun #define qb_cl(d) (&(d)->dont_manipulate_directly[0])
169