1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Andy Fleming <afleming@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun * Some part is taken from tsec.c
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <miiphy.h>
10*4882a593Smuzhiyun #include <phy.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <fsl_tgec.h>
13*4882a593Smuzhiyun #include <fm_eth.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * Write value to the PHY for this device to the register at regnum, waiting
17*4882a593Smuzhiyun * until the write is done before it returns. All PHY configuration has to be
18*4882a593Smuzhiyun * done through the TSEC1 MIIM regs
19*4882a593Smuzhiyun */
tgec_mdio_write(struct mii_dev * bus,int port_addr,int dev_addr,int regnum,u16 value)20*4882a593Smuzhiyun static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
21*4882a593Smuzhiyun int regnum, u16 value)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun u32 mdio_ctl;
24*4882a593Smuzhiyun u32 stat_val;
25*4882a593Smuzhiyun struct tgec_mdio_controller *regs = bus->priv;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun if (dev_addr == MDIO_DEVAD_NONE)
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Wait till the bus is free */
31*4882a593Smuzhiyun stat_val = MDIO_STAT_CLKDIV(100);
32*4882a593Smuzhiyun out_be32(®s->mdio_stat, stat_val);
33*4882a593Smuzhiyun while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
34*4882a593Smuzhiyun ;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Set the port and dev addr */
37*4882a593Smuzhiyun mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
38*4882a593Smuzhiyun out_be32(®s->mdio_ctl, mdio_ctl);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Set the register address */
41*4882a593Smuzhiyun out_be32(®s->mdio_addr, regnum & 0xffff);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Wait till the bus is free */
44*4882a593Smuzhiyun while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
45*4882a593Smuzhiyun ;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Write the value to the register */
48*4882a593Smuzhiyun out_be32(®s->mdio_data, MDIO_DATA(value));
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Wait till the MDIO write is complete */
51*4882a593Smuzhiyun while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
52*4882a593Smuzhiyun ;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * Reads from register regnum in the PHY for device dev, returning the value.
59*4882a593Smuzhiyun * Clears miimcom first. All PHY configuration has to be done through the
60*4882a593Smuzhiyun * TSEC1 MIIM regs
61*4882a593Smuzhiyun */
tgec_mdio_read(struct mii_dev * bus,int port_addr,int dev_addr,int regnum)62*4882a593Smuzhiyun static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
63*4882a593Smuzhiyun int regnum)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun u32 mdio_ctl;
66*4882a593Smuzhiyun u32 stat_val;
67*4882a593Smuzhiyun struct tgec_mdio_controller *regs = bus->priv;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (dev_addr == MDIO_DEVAD_NONE)
70*4882a593Smuzhiyun return 0xffff;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun stat_val = MDIO_STAT_CLKDIV(100);
73*4882a593Smuzhiyun out_be32(®s->mdio_stat, stat_val);
74*4882a593Smuzhiyun /* Wait till the bus is free */
75*4882a593Smuzhiyun while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
76*4882a593Smuzhiyun ;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Set the Port and Device Addrs */
79*4882a593Smuzhiyun mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
80*4882a593Smuzhiyun out_be32(®s->mdio_ctl, mdio_ctl);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Set the register address */
83*4882a593Smuzhiyun out_be32(®s->mdio_addr, regnum & 0xffff);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Wait till the bus is free */
86*4882a593Smuzhiyun while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
87*4882a593Smuzhiyun ;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Initiate the read */
90*4882a593Smuzhiyun mdio_ctl |= MDIO_CTL_READ;
91*4882a593Smuzhiyun out_be32(®s->mdio_ctl, mdio_ctl);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Wait till the MDIO write is complete */
94*4882a593Smuzhiyun while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
95*4882a593Smuzhiyun ;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Return all Fs if nothing was there */
98*4882a593Smuzhiyun if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
99*4882a593Smuzhiyun return 0xffff;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return in_be32(®s->mdio_data) & 0xffff;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
tgec_mdio_reset(struct mii_dev * bus)104*4882a593Smuzhiyun static int tgec_mdio_reset(struct mii_dev *bus)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
fm_tgec_mdio_init(bd_t * bis,struct tgec_mdio_info * info)109*4882a593Smuzhiyun int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct mii_dev *bus = mdio_alloc();
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (!bus) {
114*4882a593Smuzhiyun printf("Failed to allocate FM TGEC MDIO bus\n");
115*4882a593Smuzhiyun return -1;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun bus->read = tgec_mdio_read;
119*4882a593Smuzhiyun bus->write = tgec_mdio_write;
120*4882a593Smuzhiyun bus->reset = tgec_mdio_reset;
121*4882a593Smuzhiyun strcpy(bus->name, info->name);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun bus->priv = info->regs;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return mdio_register(bus);
126*4882a593Smuzhiyun }
127