1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Roy Zang <tie-fei.zang@freescale.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <phy.h>
9*4882a593Smuzhiyun #include <fm_eth.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/immap_85xx.h>
12*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun u32 port_to_devdisr[] = {
15*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
16*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
17*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
18*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
19*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
20*4882a593Smuzhiyun [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
21*4882a593Smuzhiyun [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
22*4882a593Smuzhiyun [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
23*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
24*4882a593Smuzhiyun [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
25*4882a593Smuzhiyun [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
26*4882a593Smuzhiyun [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
27*4882a593Smuzhiyun [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
28*4882a593Smuzhiyun [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
29*4882a593Smuzhiyun [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
30*4882a593Smuzhiyun [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
31*4882a593Smuzhiyun [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
32*4882a593Smuzhiyun [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
33*4882a593Smuzhiyun [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
34*4882a593Smuzhiyun [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)37*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)45*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
fman_enable_port(enum fm_port port)52*4882a593Smuzhiyun void fman_enable_port(enum fm_port port)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)59*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
62*4882a593Smuzhiyun u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (is_device_disabled(port))
65*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
68*4882a593Smuzhiyun ((is_serdes_configured(XAUI_FM1_MAC9)) ||
69*4882a593Smuzhiyun (is_serdes_configured(XAUI_FM1_MAC10)) ||
70*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC9)) ||
71*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC10))))
72*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
75*4882a593Smuzhiyun ((is_serdes_configured(XFI_FM1_MAC9)) ||
76*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC10))))
77*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
80*4882a593Smuzhiyun ((is_serdes_configured(XAUI_FM2_MAC9)) ||
81*4882a593Smuzhiyun (is_serdes_configured(XAUI_FM2_MAC10)) ||
82*4882a593Smuzhiyun (is_serdes_configured(XFI_FM2_MAC9)) ||
83*4882a593Smuzhiyun (is_serdes_configured(XFI_FM2_MAC10))))
84*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
87*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
88*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
89*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
90*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
91*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
92*4882a593Smuzhiyun #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
93*4882a593Smuzhiyun /* handle RGMII first */
94*4882a593Smuzhiyun if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
95*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
96*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
99*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
100*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
103*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
104*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
105*4882a593Smuzhiyun switch (port) {
106*4882a593Smuzhiyun case FM1_DTSEC1:
107*4882a593Smuzhiyun case FM1_DTSEC2:
108*4882a593Smuzhiyun case FM1_DTSEC3:
109*4882a593Smuzhiyun case FM1_DTSEC4:
110*4882a593Smuzhiyun case FM1_DTSEC5:
111*4882a593Smuzhiyun case FM1_DTSEC6:
112*4882a593Smuzhiyun case FM1_DTSEC9:
113*4882a593Smuzhiyun case FM1_DTSEC10:
114*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
115*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun case FM2_DTSEC1:
118*4882a593Smuzhiyun case FM2_DTSEC2:
119*4882a593Smuzhiyun case FM2_DTSEC3:
120*4882a593Smuzhiyun case FM2_DTSEC4:
121*4882a593Smuzhiyun case FM2_DTSEC5:
122*4882a593Smuzhiyun case FM2_DTSEC6:
123*4882a593Smuzhiyun case FM2_DTSEC9:
124*4882a593Smuzhiyun case FM2_DTSEC10:
125*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
126*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun default:
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* handle QSGMII */
133*4882a593Smuzhiyun switch (port) {
134*4882a593Smuzhiyun case FM1_DTSEC1:
135*4882a593Smuzhiyun case FM1_DTSEC2:
136*4882a593Smuzhiyun case FM1_DTSEC3:
137*4882a593Smuzhiyun case FM1_DTSEC4:
138*4882a593Smuzhiyun /* check lane G on SerDes1 */
139*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM1_A))
140*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
141*4882a593Smuzhiyun break;
142*4882a593Smuzhiyun case FM1_DTSEC5:
143*4882a593Smuzhiyun case FM1_DTSEC6:
144*4882a593Smuzhiyun case FM1_DTSEC9:
145*4882a593Smuzhiyun case FM1_DTSEC10:
146*4882a593Smuzhiyun /* check lane C on SerDes1 */
147*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM1_B))
148*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
149*4882a593Smuzhiyun break;
150*4882a593Smuzhiyun case FM2_DTSEC1:
151*4882a593Smuzhiyun case FM2_DTSEC2:
152*4882a593Smuzhiyun case FM2_DTSEC3:
153*4882a593Smuzhiyun case FM2_DTSEC4:
154*4882a593Smuzhiyun /* check lane G on SerDes2 */
155*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM2_A))
156*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun case FM2_DTSEC5:
159*4882a593Smuzhiyun case FM2_DTSEC6:
160*4882a593Smuzhiyun case FM2_DTSEC9:
161*4882a593Smuzhiyun case FM2_DTSEC10:
162*4882a593Smuzhiyun /* check lane C on SerDes2 */
163*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM2_B))
164*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
165*4882a593Smuzhiyun break;
166*4882a593Smuzhiyun default:
167*4882a593Smuzhiyun break;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
171*4882a593Smuzhiyun }
172