1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <phy.h>
11*4882a593Smuzhiyun #include <fm_eth.h>
12*4882a593Smuzhiyun #include <asm/immap_85xx.h>
13*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun u32 port_to_devdisr[] = {
16*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
17*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
18*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
19*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
20*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
21*4882a593Smuzhiyun [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
22*4882a593Smuzhiyun [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
23*4882a593Smuzhiyun [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
24*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
25*4882a593Smuzhiyun [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
26*4882a593Smuzhiyun [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
27*4882a593Smuzhiyun [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)30*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)38*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)45*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48*4882a593Smuzhiyun u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (is_device_disabled(port))
51*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
54*4882a593Smuzhiyun ((is_serdes_configured(XAUI_FM1_MAC9)) ||
55*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC9)) ||
56*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC10))))
57*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
60*4882a593Smuzhiyun ((is_serdes_configured(XFI_FM1_MAC1)) ||
61*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC2))))
62*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
65*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
66*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
69*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
70*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
73*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
74*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun switch (port) {
77*4882a593Smuzhiyun case FM1_DTSEC1:
78*4882a593Smuzhiyun case FM1_DTSEC2:
79*4882a593Smuzhiyun case FM1_DTSEC3:
80*4882a593Smuzhiyun case FM1_DTSEC4:
81*4882a593Smuzhiyun case FM1_DTSEC5:
82*4882a593Smuzhiyun case FM1_DTSEC6:
83*4882a593Smuzhiyun case FM1_DTSEC9:
84*4882a593Smuzhiyun case FM1_DTSEC10:
85*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
86*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun default:
89*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
93*4882a593Smuzhiyun }
94