1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #include <common.h> 7*4882a593Smuzhiyun #include <phy.h> 8*4882a593Smuzhiyun #include <fm_eth.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/immap_85xx.h> 11*4882a593Smuzhiyun #include <asm/fsl_serdes.h> 12*4882a593Smuzhiyun fman_port_enet_if(enum fm_port port)13*4882a593Smuzhiyunphy_interface_t fman_port_enet_if(enum fm_port port) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 16*4882a593Smuzhiyun u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* handle RGMII first */ 19*4882a593Smuzhiyun if ((port == FM1_DTSEC2) && 20*4882a593Smuzhiyun ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 21*4882a593Smuzhiyun FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { 22*4882a593Smuzhiyun if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 23*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 24*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 25*4882a593Smuzhiyun else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 26*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 27*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun if ((port == FM1_DTSEC4) && 31*4882a593Smuzhiyun ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 32*4882a593Smuzhiyun FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { 33*4882a593Smuzhiyun if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 34*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 35*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 36*4882a593Smuzhiyun else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 37*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 38*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII; 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun if (port == FM1_DTSEC5) { 42*4882a593Smuzhiyun if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 43*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) 44*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 45*4882a593Smuzhiyun else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 46*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) 47*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII; 48*4882a593Smuzhiyun } 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun switch (port) { 51*4882a593Smuzhiyun case FM1_DTSEC1: 52*4882a593Smuzhiyun case FM1_DTSEC2: 53*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || 54*4882a593Smuzhiyun is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) 55*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII; 56*4882a593Smuzhiyun case FM1_DTSEC3: 57*4882a593Smuzhiyun case FM1_DTSEC4: 58*4882a593Smuzhiyun case FM1_DTSEC5: 59*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 60*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII; 61*4882a593Smuzhiyun break; 62*4882a593Smuzhiyun default: 63*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 64*4882a593Smuzhiyun } 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 67*4882a593Smuzhiyun } 68