1*4882a593Smuzhiyun /* Copyright 2014 Freescale Semiconductor, Inc. 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Shengzhou Liu <Shengzhou.Liu@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <phy.h> 10*4882a593Smuzhiyun #include <fm_eth.h> 11*4882a593Smuzhiyun #include <asm/immap_85xx.h> 12*4882a593Smuzhiyun #include <asm/fsl_serdes.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun u32 port_to_devdisr[] = { 15*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun is_device_disabled(enum fm_port port)22*4882a593Smuzhiyunstatic int is_device_disabled(enum fm_port port) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 25*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun fman_disable_port(enum fm_port port)30*4882a593Smuzhiyunvoid fman_disable_port(enum fm_port port) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun fman_port_enet_if(enum fm_port port)37*4882a593Smuzhiyunphy_interface_t fman_port_enet_if(enum fm_port port) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40*4882a593Smuzhiyun u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun if (is_device_disabled(port)) 43*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) 46*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 49*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC2_RGMII) && 50*4882a593Smuzhiyun (!is_serdes_configured(QSGMII_FM1_A))) 51*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 54*4882a593Smuzhiyun FSL_CORENET_RCWSR13_EC1_RGMII) && 55*4882a593Smuzhiyun (!is_serdes_configured(QSGMII_FM1_A))) 56*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* handle SGMII */ 59*4882a593Smuzhiyun switch (port) { 60*4882a593Smuzhiyun case FM1_DTSEC1: 61*4882a593Smuzhiyun case FM1_DTSEC2: 62*4882a593Smuzhiyun case FM1_DTSEC3: 63*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 64*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII; 65*4882a593Smuzhiyun else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 66*4882a593Smuzhiyun + port - FM1_DTSEC1)) 67*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII_2500; 68*4882a593Smuzhiyun break; 69*4882a593Smuzhiyun default: 70*4882a593Smuzhiyun break; 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* handle QSGMII */ 74*4882a593Smuzhiyun switch (port) { 75*4882a593Smuzhiyun case FM1_DTSEC1: 76*4882a593Smuzhiyun case FM1_DTSEC2: 77*4882a593Smuzhiyun case FM1_DTSEC3: 78*4882a593Smuzhiyun case FM1_DTSEC4: 79*4882a593Smuzhiyun /* check lane A on SerDes1 */ 80*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM1_A)) 81*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII; 82*4882a593Smuzhiyun break; 83*4882a593Smuzhiyun default: 84*4882a593Smuzhiyun break; 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 88*4882a593Smuzhiyun } 89