1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <phy.h>
8*4882a593Smuzhiyun #include <fm_eth.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/immap_85xx.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun u32 port_to_devdisr[] = {
14*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
19*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
20*4882a593Smuzhiyun [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
21*4882a593Smuzhiyun [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
22*4882a593Smuzhiyun [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
23*4882a593Smuzhiyun [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
24*4882a593Smuzhiyun [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
25*4882a593Smuzhiyun [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)28*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
31*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)36*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* don't allow disabling of DTSEC1 as its needed for MDIO */
41*4882a593Smuzhiyun if (port == FM1_DTSEC1)
42*4882a593Smuzhiyun return;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
fman_enable_port(enum fm_port port)47*4882a593Smuzhiyun void fman_enable_port(enum fm_port port)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)54*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
57*4882a593Smuzhiyun u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (is_device_disabled(port))
60*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
63*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
66*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* handle RGMII first */
69*4882a593Smuzhiyun if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
70*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
71*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
74*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
75*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
78*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
79*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
82*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
83*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun switch (port) {
86*4882a593Smuzhiyun case FM1_DTSEC1:
87*4882a593Smuzhiyun case FM1_DTSEC2:
88*4882a593Smuzhiyun case FM1_DTSEC3:
89*4882a593Smuzhiyun case FM1_DTSEC4:
90*4882a593Smuzhiyun case FM1_DTSEC5:
91*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
92*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun case FM2_DTSEC1:
95*4882a593Smuzhiyun case FM2_DTSEC2:
96*4882a593Smuzhiyun case FM2_DTSEC3:
97*4882a593Smuzhiyun case FM2_DTSEC4:
98*4882a593Smuzhiyun case FM2_DTSEC5:
99*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
100*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
101*4882a593Smuzhiyun break;
102*4882a593Smuzhiyun default:
103*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
107*4882a593Smuzhiyun }
108