1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #include <common.h> 7*4882a593Smuzhiyun #include <phy.h> 8*4882a593Smuzhiyun #include <fm_eth.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/immap_85xx.h> 11*4882a593Smuzhiyun #include <asm/fsl_serdes.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun static u32 port_to_devdisr[] = { 14*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 15*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 16*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 17*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 18*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 19*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun is_device_disabled(enum fm_port port)22*4882a593Smuzhiyunstatic int is_device_disabled(enum fm_port port) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 25*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun fman_disable_port(enum fm_port port)30*4882a593Smuzhiyunvoid fman_disable_port(enum fm_port port) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* don't allow disabling of DTSEC1 as its needed for MDIO */ 35*4882a593Smuzhiyun if (port == FM1_DTSEC1) 36*4882a593Smuzhiyun return; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun fman_enable_port(enum fm_port port)41*4882a593Smuzhiyunvoid fman_enable_port(enum fm_port port) 42*4882a593Smuzhiyun { 43*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun fman_port_enet_if(enum fm_port port)48*4882a593Smuzhiyunphy_interface_t fman_port_enet_if(enum fm_port port) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51*4882a593Smuzhiyun u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun if (is_device_disabled(port)) 54*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 57*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* handle RGMII first */ 60*4882a593Smuzhiyun if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 61*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII)) 62*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 65*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII)) 66*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 69*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII)) 70*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 73*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII)) 74*4882a593Smuzhiyun return PHY_INTERFACE_MODE_MII; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun switch (port) { 77*4882a593Smuzhiyun case FM1_DTSEC1: 78*4882a593Smuzhiyun case FM1_DTSEC2: 79*4882a593Smuzhiyun case FM1_DTSEC3: 80*4882a593Smuzhiyun case FM1_DTSEC4: 81*4882a593Smuzhiyun case FM1_DTSEC5: 82*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 83*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII; 84*4882a593Smuzhiyun break; 85*4882a593Smuzhiyun default: 86*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 90*4882a593Smuzhiyun } 91