1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <phy.h>
8*4882a593Smuzhiyun #include <fm_eth.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/immap_85xx.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static u32 port_to_devdisr[] = {
14*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
19*4882a593Smuzhiyun [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
20*4882a593Smuzhiyun [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
21*4882a593Smuzhiyun [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
22*4882a593Smuzhiyun [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
23*4882a593Smuzhiyun [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)26*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
29*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)34*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* don't allow disabling of DTSEC1 as its needed for MDIO */
39*4882a593Smuzhiyun if (port == FM1_DTSEC1)
40*4882a593Smuzhiyun return;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
fman_enable_port(enum fm_port port)45*4882a593Smuzhiyun void fman_enable_port(enum fm_port port)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)52*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55*4882a593Smuzhiyun u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (is_device_disabled(port))
58*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
61*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
64*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* handle RGMII first */
67*4882a593Smuzhiyun if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
68*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
69*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
72*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
73*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
76*4882a593Smuzhiyun FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
77*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun switch (port) {
80*4882a593Smuzhiyun case FM1_DTSEC1:
81*4882a593Smuzhiyun case FM1_DTSEC2:
82*4882a593Smuzhiyun case FM1_DTSEC3:
83*4882a593Smuzhiyun case FM1_DTSEC4:
84*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
85*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
86*4882a593Smuzhiyun break;
87*4882a593Smuzhiyun case FM2_DTSEC1:
88*4882a593Smuzhiyun case FM2_DTSEC2:
89*4882a593Smuzhiyun case FM2_DTSEC3:
90*4882a593Smuzhiyun case FM2_DTSEC4:
91*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
92*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun default:
95*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
99*4882a593Smuzhiyun }
100