1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #include <common.h> 7*4882a593Smuzhiyun #include <phy.h> 8*4882a593Smuzhiyun #include <fm_eth.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/immap_85xx.h> 11*4882a593Smuzhiyun #include <asm/fsl_serdes.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun static u32 port_to_devdisr[] = { 14*4882a593Smuzhiyun [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1, 15*4882a593Smuzhiyun [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2, 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun is_device_disabled(enum fm_port port)18*4882a593Smuzhiyunstatic int is_device_disabled(enum fm_port port) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 21*4882a593Smuzhiyun u32 devdisr = in_be32(&gur->devdisr); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr; 24*4882a593Smuzhiyun } 25*4882a593Smuzhiyun fman_disable_port(enum fm_port port)26*4882a593Smuzhiyunvoid fman_disable_port(enum fm_port port) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* don't allow disabling of DTSEC1 as its needed for MDIO */ 31*4882a593Smuzhiyun if (port == FM1_DTSEC1) 32*4882a593Smuzhiyun return; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun setbits_be32(&gur->devdisr, port_to_devdisr[port]); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun fman_enable_port(enum fm_port port)37*4882a593Smuzhiyunvoid fman_enable_port(enum fm_port port) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clrbits_be32(&gur->devdisr, port_to_devdisr[port]); 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun fman_port_enet_if(enum fm_port port)44*4882a593Smuzhiyunphy_interface_t fman_port_enet_if(enum fm_port port) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 47*4882a593Smuzhiyun u32 pordevsr = in_be32(&gur->pordevsr); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun if (is_device_disabled(port)) 50*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* DTSEC1 can be SGMII, RGMII or RMII */ 53*4882a593Smuzhiyun if (port == FM1_DTSEC1) { 54*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1)) 55*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII; 56*4882a593Smuzhiyun if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) { 57*4882a593Smuzhiyun if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC) 58*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 59*4882a593Smuzhiyun else 60*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RMII; 61*4882a593Smuzhiyun } 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* DTSEC2 only supports SGMII or RGMII */ 65*4882a593Smuzhiyun if (port == FM1_DTSEC2) { 66*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC2)) 67*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII; 68*4882a593Smuzhiyun if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS) 69*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII; 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE; 73*4882a593Smuzhiyun } 74