1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <phy.h>
8*4882a593Smuzhiyun #include <fm_eth.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
13*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
14*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
15*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
16*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
17*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
18*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
19*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
20*4882a593Smuzhiyun #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun u32 port_to_devdisr[] = {
23*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
24*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
25*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
26*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
27*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
28*4882a593Smuzhiyun [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
29*4882a593Smuzhiyun [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
30*4882a593Smuzhiyun [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
31*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
32*4882a593Smuzhiyun [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
33*4882a593Smuzhiyun [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
34*4882a593Smuzhiyun [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)37*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
40*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)45*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)52*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
55*4882a593Smuzhiyun u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (is_device_disabled(port))
58*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
61*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
64*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
67*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
70*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (port == FM1_DTSEC3)
73*4882a593Smuzhiyun if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
74*4882a593Smuzhiyun FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
75*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII_TXID;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (port == FM1_DTSEC4)
78*4882a593Smuzhiyun if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
79*4882a593Smuzhiyun FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
80*4882a593Smuzhiyun return PHY_INTERFACE_MODE_RGMII_TXID;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* handle SGMII, only MAC 2/5/6/9/10 available */
83*4882a593Smuzhiyun switch (port) {
84*4882a593Smuzhiyun case FM1_DTSEC2:
85*4882a593Smuzhiyun case FM1_DTSEC5:
86*4882a593Smuzhiyun case FM1_DTSEC6:
87*4882a593Smuzhiyun case FM1_DTSEC9:
88*4882a593Smuzhiyun case FM1_DTSEC10:
89*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
90*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun default:
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* handle 2.5G SGMII, only MAC 5/9/10 available */
97*4882a593Smuzhiyun switch (port) {
98*4882a593Smuzhiyun case FM1_DTSEC5:
99*4882a593Smuzhiyun case FM1_DTSEC9:
100*4882a593Smuzhiyun case FM1_DTSEC10:
101*4882a593Smuzhiyun if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
102*4882a593Smuzhiyun port - FM1_DTSEC5))
103*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII_2500;
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun default:
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* handle QSGMII, only MAC 1/5/6/10 available */
110*4882a593Smuzhiyun switch (port) {
111*4882a593Smuzhiyun case FM1_DTSEC1:
112*4882a593Smuzhiyun case FM1_DTSEC5:
113*4882a593Smuzhiyun case FM1_DTSEC6:
114*4882a593Smuzhiyun case FM1_DTSEC10:
115*4882a593Smuzhiyun if (is_serdes_configured(QSGMII_FM1_A))
116*4882a593Smuzhiyun return PHY_INTERFACE_MODE_QSGMII;
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun default:
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
123*4882a593Smuzhiyun }
124