1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FM_H__ 8*4882a593Smuzhiyun #define __FM_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <phy.h> 12*4882a593Smuzhiyun #include <fm_eth.h> 13*4882a593Smuzhiyun #include <fsl_fman.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Port ID */ 16*4882a593Smuzhiyun #define OH_PORT_ID_BASE 0x01 17*4882a593Smuzhiyun #define MAX_NUM_OH_PORT 7 18*4882a593Smuzhiyun #define RX_PORT_1G_BASE 0x08 19*4882a593Smuzhiyun #define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC 20*4882a593Smuzhiyun #define RX_PORT_10G_BASE 0x10 21*4882a593Smuzhiyun #define RX_PORT_10G_BASE2 0x08 22*4882a593Smuzhiyun #define TX_PORT_1G_BASE 0x28 23*4882a593Smuzhiyun #define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC 24*4882a593Smuzhiyun #define TX_PORT_10G_BASE 0x30 25*4882a593Smuzhiyun #define TX_PORT_10G_BASE2 0x28 26*4882a593Smuzhiyun #define MIIM_TIMEOUT 0xFFFF 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct fm_muram { 29*4882a593Smuzhiyun void *base; 30*4882a593Smuzhiyun void *top; 31*4882a593Smuzhiyun size_t size; 32*4882a593Smuzhiyun void *alloc; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun #define FM_MURAM_RES_SIZE 0x01000 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Rx/Tx buffer descriptor */ 37*4882a593Smuzhiyun struct fm_port_bd { 38*4882a593Smuzhiyun u16 status; 39*4882a593Smuzhiyun u16 len; 40*4882a593Smuzhiyun u32 res0; 41*4882a593Smuzhiyun u16 res1; 42*4882a593Smuzhiyun u16 buf_ptr_hi; 43*4882a593Smuzhiyun u32 buf_ptr_lo; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Common BD flags */ 47*4882a593Smuzhiyun #define BD_LAST 0x0800 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Rx BD status flags */ 50*4882a593Smuzhiyun #define RxBD_EMPTY 0x8000 51*4882a593Smuzhiyun #define RxBD_LAST BD_LAST 52*4882a593Smuzhiyun #define RxBD_FIRST 0x0400 53*4882a593Smuzhiyun #define RxBD_PHYS_ERR 0x0008 54*4882a593Smuzhiyun #define RxBD_SIZE_ERR 0x0004 55*4882a593Smuzhiyun #define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Tx BD status flags */ 58*4882a593Smuzhiyun #define TxBD_READY 0x8000 59*4882a593Smuzhiyun #define TxBD_LAST BD_LAST 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Rx/Tx queue descriptor */ 62*4882a593Smuzhiyun struct fm_port_qd { 63*4882a593Smuzhiyun u16 gen; 64*4882a593Smuzhiyun u16 bd_ring_base_hi; 65*4882a593Smuzhiyun u32 bd_ring_base_lo; 66*4882a593Smuzhiyun u16 bd_ring_size; 67*4882a593Smuzhiyun u16 offset_in; 68*4882a593Smuzhiyun u16 offset_out; 69*4882a593Smuzhiyun u16 res0; 70*4882a593Smuzhiyun u32 res1[0x4]; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* IM global parameter RAM */ 74*4882a593Smuzhiyun struct fm_port_global_pram { 75*4882a593Smuzhiyun u32 mode; /* independent mode register */ 76*4882a593Smuzhiyun u32 rxqd_ptr; /* Rx queue descriptor pointer */ 77*4882a593Smuzhiyun u32 txqd_ptr; /* Tx queue descriptor pointer */ 78*4882a593Smuzhiyun u16 mrblr; /* max Rx buffer length */ 79*4882a593Smuzhiyun u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */ 80*4882a593Smuzhiyun u32 res0[0x4]; 81*4882a593Smuzhiyun struct fm_port_qd rxqd; /* Rx queue descriptor */ 82*4882a593Smuzhiyun struct fm_port_qd txqd; /* Tx queue descriptor */ 83*4882a593Smuzhiyun u32 res1[0x28]; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define FM_PRAM_SIZE sizeof(struct fm_port_global_pram) 87*4882a593Smuzhiyun #define FM_PRAM_ALIGN 256 88*4882a593Smuzhiyun #define PRAM_MODE_GLOBAL 0x20000000 89*4882a593Smuzhiyun #define PRAM_MODE_GRACEFUL_STOP 0x00800000 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #if defined(CONFIG_ARCH_P1023) 92*4882a593Smuzhiyun #define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */ 93*4882a593Smuzhiyun #else 94*4882a593Smuzhiyun #define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */ 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun #define FM_FREE_POOL_ALIGN 256 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun void *fm_muram_alloc(int fm_idx, size_t size, ulong align); 99*4882a593Smuzhiyun void *fm_muram_base(int fm_idx); 100*4882a593Smuzhiyun int fm_init_common(int index, struct ccsr_fman *reg); 101*4882a593Smuzhiyun int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); 102*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port); 103*4882a593Smuzhiyun void fman_disable_port(enum fm_port port); 104*4882a593Smuzhiyun void fman_enable_port(enum fm_port port); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct fsl_enet_mac { 107*4882a593Smuzhiyun void *base; /* MAC controller registers base address */ 108*4882a593Smuzhiyun void *phyregs; 109*4882a593Smuzhiyun int max_rx_len; 110*4882a593Smuzhiyun void (*init_mac)(struct fsl_enet_mac *mac); 111*4882a593Smuzhiyun void (*enable_mac)(struct fsl_enet_mac *mac); 112*4882a593Smuzhiyun void (*disable_mac)(struct fsl_enet_mac *mac); 113*4882a593Smuzhiyun void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr); 114*4882a593Smuzhiyun void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type, 115*4882a593Smuzhiyun int speed); 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Fman ethernet private struct */ 119*4882a593Smuzhiyun struct fm_eth { 120*4882a593Smuzhiyun int fm_index; /* Fman index */ 121*4882a593Smuzhiyun u32 num; /* 0..n-1 for give type */ 122*4882a593Smuzhiyun struct fm_bmi_tx_port *tx_port; 123*4882a593Smuzhiyun struct fm_bmi_rx_port *rx_port; 124*4882a593Smuzhiyun enum fm_eth_type type; /* 1G or 10G ethernet */ 125*4882a593Smuzhiyun phy_interface_t enet_if; 126*4882a593Smuzhiyun struct fsl_enet_mac *mac; /* MAC controller */ 127*4882a593Smuzhiyun struct mii_dev *bus; 128*4882a593Smuzhiyun struct phy_device *phydev; 129*4882a593Smuzhiyun int phyaddr; 130*4882a593Smuzhiyun struct eth_device *dev; 131*4882a593Smuzhiyun int max_rx_len; 132*4882a593Smuzhiyun struct fm_port_global_pram *rx_pram; /* Rx parameter table */ 133*4882a593Smuzhiyun struct fm_port_global_pram *tx_pram; /* Tx parameter table */ 134*4882a593Smuzhiyun void *rx_bd_ring; /* Rx BD ring base */ 135*4882a593Smuzhiyun void *cur_rxbd; /* current Rx BD */ 136*4882a593Smuzhiyun void *rx_buf; /* Rx buffer base */ 137*4882a593Smuzhiyun void *tx_bd_ring; /* Tx BD ring base */ 138*4882a593Smuzhiyun void *cur_txbd; /* current Tx BD */ 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define RX_BD_RING_SIZE 8 142*4882a593Smuzhiyun #define TX_BD_RING_SIZE 8 143*4882a593Smuzhiyun #define MAX_RXBUF_LOG2 11 144*4882a593Smuzhiyun #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ 147*4882a593Smuzhiyun 0 : fm_info[fm_port_to_index(port)].enabled) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #endif /* __FM_H__ */ 150