1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Roy Zang <tie-fei.zang@freescale.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <phy.h>
9*4882a593Smuzhiyun #include <fm_eth.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/immap_85xx.h>
12*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
13*4882a593Smuzhiyun #include <hwconfig.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun u32 port_to_devdisr[] = {
16*4882a593Smuzhiyun [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
17*4882a593Smuzhiyun [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
18*4882a593Smuzhiyun [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
19*4882a593Smuzhiyun [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
20*4882a593Smuzhiyun [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
21*4882a593Smuzhiyun [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
22*4882a593Smuzhiyun [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
23*4882a593Smuzhiyun [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
is_device_disabled(enum fm_port port)26*4882a593Smuzhiyun static int is_device_disabled(enum fm_port port)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
29*4882a593Smuzhiyun u32 devdisr2 = in_be32(&gur->devdisr2);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return port_to_devdisr[port] & devdisr2;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
fman_disable_port(enum fm_port port)34*4882a593Smuzhiyun void fman_disable_port(enum fm_port port)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
fman_enable_port(enum fm_port port)41*4882a593Smuzhiyun void fman_enable_port(enum fm_port port)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
fman_port_enet_if(enum fm_port port)48*4882a593Smuzhiyun phy_interface_t fman_port_enet_if(enum fm_port port)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
51*4882a593Smuzhiyun u32 serdes2_prtcl;
52*4882a593Smuzhiyun char buffer[HWCONFIG_BUFFER_SIZE];
53*4882a593Smuzhiyun char *buf = NULL;
54*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (is_device_disabled(port))
58*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*B4860 has two 10Gig Mac*/
61*4882a593Smuzhiyun if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
62*4882a593Smuzhiyun ((is_serdes_configured(XAUI_FM1_MAC9)) ||
63*4882a593Smuzhiyun #if (!defined(CONFIG_TARGET_B4860QDS) && \
64*4882a593Smuzhiyun !defined(CONFIG_TARGET_B4R420QDS))
65*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC9)) ||
66*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC10)) ||
67*4882a593Smuzhiyun #endif
68*4882a593Smuzhiyun (is_serdes_configured(XAUI_FM1_MAC10))
69*4882a593Smuzhiyun ))
70*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
73*4882a593Smuzhiyun serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
74*4882a593Smuzhiyun FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (serdes2_prtcl) {
77*4882a593Smuzhiyun serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
78*4882a593Smuzhiyun switch (serdes2_prtcl) {
79*4882a593Smuzhiyun case 0x80:
80*4882a593Smuzhiyun case 0x81:
81*4882a593Smuzhiyun case 0x82:
82*4882a593Smuzhiyun case 0x83:
83*4882a593Smuzhiyun case 0x84:
84*4882a593Smuzhiyun case 0x85:
85*4882a593Smuzhiyun case 0x86:
86*4882a593Smuzhiyun case 0x87:
87*4882a593Smuzhiyun case 0x88:
88*4882a593Smuzhiyun case 0x89:
89*4882a593Smuzhiyun case 0x8a:
90*4882a593Smuzhiyun case 0x8b:
91*4882a593Smuzhiyun case 0x8c:
92*4882a593Smuzhiyun case 0x8d:
93*4882a593Smuzhiyun case 0x8e:
94*4882a593Smuzhiyun case 0xb1:
95*4882a593Smuzhiyun case 0xb2:
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * Extract hwconfig from environment since environment
98*4882a593Smuzhiyun * is not setup yet
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun env_get_f("hwconfig", buffer, sizeof(buffer));
101*4882a593Smuzhiyun buf = buffer;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* check if XFI interface enable in hwconfig for 10g */
104*4882a593Smuzhiyun if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
105*4882a593Smuzhiyun "sfp_amc", "sfp", buf)) {
106*4882a593Smuzhiyun if ((port == FM1_10GEC1 ||
107*4882a593Smuzhiyun port == FM1_10GEC2) &&
108*4882a593Smuzhiyun ((is_serdes_configured(XFI_FM1_MAC9)) ||
109*4882a593Smuzhiyun (is_serdes_configured(XFI_FM1_MAC10))))
110*4882a593Smuzhiyun return PHY_INTERFACE_MODE_XGMII;
111*4882a593Smuzhiyun else if ((port == FM1_DTSEC1) ||
112*4882a593Smuzhiyun (port == FM1_DTSEC2) ||
113*4882a593Smuzhiyun (port == FM1_DTSEC3) ||
114*4882a593Smuzhiyun (port == FM1_DTSEC4))
115*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Fix me need to handle RGMII here first */
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun switch (port) {
124*4882a593Smuzhiyun case FM1_DTSEC1:
125*4882a593Smuzhiyun case FM1_DTSEC2:
126*4882a593Smuzhiyun case FM1_DTSEC3:
127*4882a593Smuzhiyun case FM1_DTSEC4:
128*4882a593Smuzhiyun case FM1_DTSEC5:
129*4882a593Smuzhiyun case FM1_DTSEC6:
130*4882a593Smuzhiyun if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
131*4882a593Smuzhiyun return PHY_INTERFACE_MODE_SGMII;
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun default:
134*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return PHY_INTERFACE_MODE_NONE;
138*4882a593Smuzhiyun }
139