1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004, 2005 5*4882a593Smuzhiyun * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _EP93XX_ETH_H 11*4882a593Smuzhiyun #define _EP93XX_ETH_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <net.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /** 16*4882a593Smuzhiyun * #define this to dump device status and queue info during initialization and 17*4882a593Smuzhiyun * following errors. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #undef EP93XX_MAC_DEBUG 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /** 22*4882a593Smuzhiyun * Number of descriptor and status entries in our RX queues. 23*4882a593Smuzhiyun * It must be power of 2 ! 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define NUMRXDESC PKTBUFSRX 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /** 28*4882a593Smuzhiyun * Number of descriptor and status entries in our TX queues. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define NUMTXDESC 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /** 33*4882a593Smuzhiyun * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define TXSTARTMAX 944 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * Receive descriptor queue entry 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun struct rx_descriptor { 41*4882a593Smuzhiyun uint32_t word1; 42*4882a593Smuzhiyun uint32_t word2; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /** 46*4882a593Smuzhiyun * Receive status queue entry 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun struct rx_status { 49*4882a593Smuzhiyun uint32_t word1; 50*4882a593Smuzhiyun uint32_t word2; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) 54*4882a593Smuzhiyun #define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) 55*4882a593Smuzhiyun #define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /** 58*4882a593Smuzhiyun * Transmit descriptor queue entry 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun struct tx_descriptor { 61*4882a593Smuzhiyun uint32_t word1; 62*4882a593Smuzhiyun uint32_t word2; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define TX_DESC_EOF (1 << 31) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /** 68*4882a593Smuzhiyun * Transmit status queue entry 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun struct tx_status { 71*4882a593Smuzhiyun uint32_t word1; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) 75*4882a593Smuzhiyun #define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /** 78*4882a593Smuzhiyun * Transmit descriptor queue 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun struct tx_descriptor_queue { 81*4882a593Smuzhiyun struct tx_descriptor *base; 82*4882a593Smuzhiyun struct tx_descriptor *current; 83*4882a593Smuzhiyun struct tx_descriptor *end; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /** 87*4882a593Smuzhiyun * Transmit status queue 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun struct tx_status_queue { 90*4882a593Smuzhiyun struct tx_status *base; 91*4882a593Smuzhiyun volatile struct tx_status *current; 92*4882a593Smuzhiyun struct tx_status *end; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /** 96*4882a593Smuzhiyun * Receive descriptor queue 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun struct rx_descriptor_queue { 99*4882a593Smuzhiyun struct rx_descriptor *base; 100*4882a593Smuzhiyun struct rx_descriptor *current; 101*4882a593Smuzhiyun struct rx_descriptor *end; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /** 105*4882a593Smuzhiyun * Receive status queue 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun struct rx_status_queue { 108*4882a593Smuzhiyun struct rx_status *base; 109*4882a593Smuzhiyun volatile struct rx_status *current; 110*4882a593Smuzhiyun struct rx_status *end; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /** 114*4882a593Smuzhiyun * EP93xx MAC private data structure 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun struct ep93xx_priv { 117*4882a593Smuzhiyun struct rx_descriptor_queue rx_dq; 118*4882a593Smuzhiyun struct rx_status_queue rx_sq; 119*4882a593Smuzhiyun void *rx_buffer[NUMRXDESC]; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun struct tx_descriptor_queue tx_dq; 122*4882a593Smuzhiyun struct tx_status_queue tx_sq; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun struct mac_regs *regs; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif 128