1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (X) extracted from enc28j60.c 3*4882a593Smuzhiyun * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _enc28j60_h 9*4882a593Smuzhiyun #define _enc28j60_h 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * SPI Commands 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Bits 7-5: Command 15*4882a593Smuzhiyun * Bits 4-0: Register 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */ 18*4882a593Smuzhiyun #define CMD_RBM 0x3a /* Read Buffer Memory */ 19*4882a593Smuzhiyun #define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */ 20*4882a593Smuzhiyun #define CMD_WBM 0x7a /* Write Buffer Memory */ 21*4882a593Smuzhiyun #define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */ 22*4882a593Smuzhiyun #define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */ 23*4882a593Smuzhiyun #define CMD_SRC 0xff /* System Reset Command */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* NEW: encode (bank number+1) in upper byte */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Common Control Registers accessible in all Banks */ 28*4882a593Smuzhiyun #define CTL_REG_EIE 0x01B 29*4882a593Smuzhiyun #define CTL_REG_EIR 0x01C 30*4882a593Smuzhiyun #define CTL_REG_ESTAT 0x01D 31*4882a593Smuzhiyun #define CTL_REG_ECON2 0x01E 32*4882a593Smuzhiyun #define CTL_REG_ECON1 0x01F 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Control Registers accessible in Bank 0 */ 35*4882a593Smuzhiyun #define CTL_REG_ERDPTL 0x100 36*4882a593Smuzhiyun #define CTL_REG_ERDPTH 0x101 37*4882a593Smuzhiyun #define CTL_REG_EWRPTL 0x102 38*4882a593Smuzhiyun #define CTL_REG_EWRPTH 0x103 39*4882a593Smuzhiyun #define CTL_REG_ETXSTL 0x104 40*4882a593Smuzhiyun #define CTL_REG_ETXSTH 0x105 41*4882a593Smuzhiyun #define CTL_REG_ETXNDL 0x106 42*4882a593Smuzhiyun #define CTL_REG_ETXNDH 0x107 43*4882a593Smuzhiyun #define CTL_REG_ERXSTL 0x108 44*4882a593Smuzhiyun #define CTL_REG_ERXSTH 0x109 45*4882a593Smuzhiyun #define CTL_REG_ERXNDL 0x10A 46*4882a593Smuzhiyun #define CTL_REG_ERXNDH 0x10B 47*4882a593Smuzhiyun #define CTL_REG_ERXRDPTL 0x10C 48*4882a593Smuzhiyun #define CTL_REG_ERXRDPTH 0x10D 49*4882a593Smuzhiyun #define CTL_REG_ERXWRPTL 0x10E 50*4882a593Smuzhiyun #define CTL_REG_ERXWRPTH 0x10F 51*4882a593Smuzhiyun #define CTL_REG_EDMASTL 0x110 52*4882a593Smuzhiyun #define CTL_REG_EDMASTH 0x111 53*4882a593Smuzhiyun #define CTL_REG_EDMANDL 0x112 54*4882a593Smuzhiyun #define CTL_REG_EDMANDH 0x113 55*4882a593Smuzhiyun #define CTL_REG_EDMADSTL 0x114 56*4882a593Smuzhiyun #define CTL_REG_EDMADSTH 0x115 57*4882a593Smuzhiyun #define CTL_REG_EDMACSL 0x116 58*4882a593Smuzhiyun #define CTL_REG_EDMACSH 0x117 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Control Registers accessible in Bank 1 */ 61*4882a593Smuzhiyun #define CTL_REG_EHT0 0x200 62*4882a593Smuzhiyun #define CTL_REG_EHT1 0x201 63*4882a593Smuzhiyun #define CTL_REG_EHT2 0x202 64*4882a593Smuzhiyun #define CTL_REG_EHT3 0x203 65*4882a593Smuzhiyun #define CTL_REG_EHT4 0x204 66*4882a593Smuzhiyun #define CTL_REG_EHT5 0x205 67*4882a593Smuzhiyun #define CTL_REG_EHT6 0x206 68*4882a593Smuzhiyun #define CTL_REG_EHT7 0x207 69*4882a593Smuzhiyun #define CTL_REG_EPMM0 0x208 70*4882a593Smuzhiyun #define CTL_REG_EPMM1 0x209 71*4882a593Smuzhiyun #define CTL_REG_EPMM2 0x20A 72*4882a593Smuzhiyun #define CTL_REG_EPMM3 0x20B 73*4882a593Smuzhiyun #define CTL_REG_EPMM4 0x20C 74*4882a593Smuzhiyun #define CTL_REG_EPMM5 0x20D 75*4882a593Smuzhiyun #define CTL_REG_EPMM6 0x20E 76*4882a593Smuzhiyun #define CTL_REG_EPMM7 0x20F 77*4882a593Smuzhiyun #define CTL_REG_EPMCSL 0x210 78*4882a593Smuzhiyun #define CTL_REG_EPMCSH 0x211 79*4882a593Smuzhiyun #define CTL_REG_EPMOL 0x214 80*4882a593Smuzhiyun #define CTL_REG_EPMOH 0x215 81*4882a593Smuzhiyun #define CTL_REG_EWOLIE 0x216 82*4882a593Smuzhiyun #define CTL_REG_EWOLIR 0x217 83*4882a593Smuzhiyun #define CTL_REG_ERXFCON 0x218 84*4882a593Smuzhiyun #define CTL_REG_EPKTCNT 0x219 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Control Registers accessible in Bank 2 */ 87*4882a593Smuzhiyun #define CTL_REG_MACON1 0x300 88*4882a593Smuzhiyun #define CTL_REG_MACON2 0x301 89*4882a593Smuzhiyun #define CTL_REG_MACON3 0x302 90*4882a593Smuzhiyun #define CTL_REG_MACON4 0x303 91*4882a593Smuzhiyun #define CTL_REG_MABBIPG 0x304 92*4882a593Smuzhiyun #define CTL_REG_MAIPGL 0x306 93*4882a593Smuzhiyun #define CTL_REG_MAIPGH 0x307 94*4882a593Smuzhiyun #define CTL_REG_MACLCON1 0x308 95*4882a593Smuzhiyun #define CTL_REG_MACLCON2 0x309 96*4882a593Smuzhiyun #define CTL_REG_MAMXFLL 0x30A 97*4882a593Smuzhiyun #define CTL_REG_MAMXFLH 0x30B 98*4882a593Smuzhiyun #define CTL_REG_MAPHSUP 0x30D 99*4882a593Smuzhiyun #define CTL_REG_MICON 0x311 100*4882a593Smuzhiyun #define CTL_REG_MICMD 0x312 101*4882a593Smuzhiyun #define CTL_REG_MIREGADR 0x314 102*4882a593Smuzhiyun #define CTL_REG_MIWRL 0x316 103*4882a593Smuzhiyun #define CTL_REG_MIWRH 0x317 104*4882a593Smuzhiyun #define CTL_REG_MIRDL 0x318 105*4882a593Smuzhiyun #define CTL_REG_MIRDH 0x319 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Control Registers accessible in Bank 3 */ 108*4882a593Smuzhiyun #define CTL_REG_MAADR1 0x400 109*4882a593Smuzhiyun #define CTL_REG_MAADR0 0x401 110*4882a593Smuzhiyun #define CTL_REG_MAADR3 0x402 111*4882a593Smuzhiyun #define CTL_REG_MAADR2 0x403 112*4882a593Smuzhiyun #define CTL_REG_MAADR5 0x404 113*4882a593Smuzhiyun #define CTL_REG_MAADR4 0x405 114*4882a593Smuzhiyun #define CTL_REG_EBSTSD 0x406 115*4882a593Smuzhiyun #define CTL_REG_EBSTCON 0x407 116*4882a593Smuzhiyun #define CTL_REG_EBSTCSL 0x408 117*4882a593Smuzhiyun #define CTL_REG_EBSTCSH 0x409 118*4882a593Smuzhiyun #define CTL_REG_MISTAT 0x40A 119*4882a593Smuzhiyun #define CTL_REG_EREVID 0x412 120*4882a593Smuzhiyun #define CTL_REG_ECOCON 0x415 121*4882a593Smuzhiyun #define CTL_REG_EFLOCON 0x417 122*4882a593Smuzhiyun #define CTL_REG_EPAUSL 0x418 123*4882a593Smuzhiyun #define CTL_REG_EPAUSH 0x419 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* PHY Register */ 126*4882a593Smuzhiyun #define PHY_REG_PHCON1 0x00 127*4882a593Smuzhiyun #define PHY_REG_PHSTAT1 0x01 128*4882a593Smuzhiyun #define PHY_REG_PHID1 0x02 129*4882a593Smuzhiyun #define PHY_REG_PHID2 0x03 130*4882a593Smuzhiyun #define PHY_REG_PHCON2 0x10 131*4882a593Smuzhiyun #define PHY_REG_PHSTAT2 0x11 132*4882a593Smuzhiyun #define PHY_REG_PHLCON 0x14 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* Receive Filter Register (ERXFCON) bits */ 135*4882a593Smuzhiyun #define ENC_RFR_UCEN 0x80 136*4882a593Smuzhiyun #define ENC_RFR_ANDOR 0x40 137*4882a593Smuzhiyun #define ENC_RFR_CRCEN 0x20 138*4882a593Smuzhiyun #define ENC_RFR_PMEN 0x10 139*4882a593Smuzhiyun #define ENC_RFR_MPEN 0x08 140*4882a593Smuzhiyun #define ENC_RFR_HTEN 0x04 141*4882a593Smuzhiyun #define ENC_RFR_MCEN 0x02 142*4882a593Smuzhiyun #define ENC_RFR_BCEN 0x01 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* ECON1 Register Bits */ 145*4882a593Smuzhiyun #define ENC_ECON1_TXRST 0x80 146*4882a593Smuzhiyun #define ENC_ECON1_RXRST 0x40 147*4882a593Smuzhiyun #define ENC_ECON1_DMAST 0x20 148*4882a593Smuzhiyun #define ENC_ECON1_CSUMEN 0x10 149*4882a593Smuzhiyun #define ENC_ECON1_TXRTS 0x08 150*4882a593Smuzhiyun #define ENC_ECON1_RXEN 0x04 151*4882a593Smuzhiyun #define ENC_ECON1_BSEL1 0x02 152*4882a593Smuzhiyun #define ENC_ECON1_BSEL0 0x01 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* ECON2 Register Bits */ 155*4882a593Smuzhiyun #define ENC_ECON2_AUTOINC 0x80 156*4882a593Smuzhiyun #define ENC_ECON2_PKTDEC 0x40 157*4882a593Smuzhiyun #define ENC_ECON2_PWRSV 0x20 158*4882a593Smuzhiyun #define ENC_ECON2_VRPS 0x08 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* EIR Register Bits */ 161*4882a593Smuzhiyun #define ENC_EIR_PKTIF 0x40 162*4882a593Smuzhiyun #define ENC_EIR_DMAIF 0x20 163*4882a593Smuzhiyun #define ENC_EIR_LINKIF 0x10 164*4882a593Smuzhiyun #define ENC_EIR_TXIF 0x08 165*4882a593Smuzhiyun #define ENC_EIR_WOLIF 0x04 166*4882a593Smuzhiyun #define ENC_EIR_TXERIF 0x02 167*4882a593Smuzhiyun #define ENC_EIR_RXERIF 0x01 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* ESTAT Register Bits */ 170*4882a593Smuzhiyun #define ENC_ESTAT_INT 0x80 171*4882a593Smuzhiyun #define ENC_ESTAT_LATECOL 0x10 172*4882a593Smuzhiyun #define ENC_ESTAT_RXBUSY 0x04 173*4882a593Smuzhiyun #define ENC_ESTAT_TXABRT 0x02 174*4882a593Smuzhiyun #define ENC_ESTAT_CLKRDY 0x01 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* EIE Register Bits */ 177*4882a593Smuzhiyun #define ENC_EIE_INTIE 0x80 178*4882a593Smuzhiyun #define ENC_EIE_PKTIE 0x40 179*4882a593Smuzhiyun #define ENC_EIE_DMAIE 0x20 180*4882a593Smuzhiyun #define ENC_EIE_LINKIE 0x10 181*4882a593Smuzhiyun #define ENC_EIE_TXIE 0x08 182*4882a593Smuzhiyun #define ENC_EIE_WOLIE 0x04 183*4882a593Smuzhiyun #define ENC_EIE_TXERIE 0x02 184*4882a593Smuzhiyun #define ENC_EIE_RXERIE 0x01 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* MACON1 Register Bits */ 187*4882a593Smuzhiyun #define ENC_MACON1_LOOPBK 0x10 188*4882a593Smuzhiyun #define ENC_MACON1_TXPAUS 0x08 189*4882a593Smuzhiyun #define ENC_MACON1_RXPAUS 0x04 190*4882a593Smuzhiyun #define ENC_MACON1_PASSALL 0x02 191*4882a593Smuzhiyun #define ENC_MACON1_MARXEN 0x01 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* MACON2 Register Bits */ 194*4882a593Smuzhiyun #define ENC_MACON2_MARST 0x80 195*4882a593Smuzhiyun #define ENC_MACON2_RNDRST 0x40 196*4882a593Smuzhiyun #define ENC_MACON2_MARXRST 0x08 197*4882a593Smuzhiyun #define ENC_MACON2_RFUNRST 0x04 198*4882a593Smuzhiyun #define ENC_MACON2_MATXRST 0x02 199*4882a593Smuzhiyun #define ENC_MACON2_TFUNRST 0x01 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* MACON3 Register Bits */ 202*4882a593Smuzhiyun #define ENC_MACON3_PADCFG2 0x80 203*4882a593Smuzhiyun #define ENC_MACON3_PADCFG1 0x40 204*4882a593Smuzhiyun #define ENC_MACON3_PADCFG0 0x20 205*4882a593Smuzhiyun #define ENC_MACON3_TXCRCEN 0x10 206*4882a593Smuzhiyun #define ENC_MACON3_PHDRLEN 0x08 207*4882a593Smuzhiyun #define ENC_MACON3_HFRMEN 0x04 208*4882a593Smuzhiyun #define ENC_MACON3_FRMLNEN 0x02 209*4882a593Smuzhiyun #define ENC_MACON3_FULDPX 0x01 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* MACON4 Register Bits */ 212*4882a593Smuzhiyun #define ENC_MACON4_DEFER 0x40 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* MICMD Register Bits */ 215*4882a593Smuzhiyun #define ENC_MICMD_MIISCAN 0x02 216*4882a593Smuzhiyun #define ENC_MICMD_MIIRD 0x01 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* MISTAT Register Bits */ 219*4882a593Smuzhiyun #define ENC_MISTAT_NVALID 0x04 220*4882a593Smuzhiyun #define ENC_MISTAT_SCAN 0x02 221*4882a593Smuzhiyun #define ENC_MISTAT_BUSY 0x01 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* PHID1 and PHID2 values */ 224*4882a593Smuzhiyun #define ENC_PHID1_VALUE 0x0083 225*4882a593Smuzhiyun #define ENC_PHID2_VALUE 0x1400 226*4882a593Smuzhiyun #define ENC_PHID2_MASK 0xFC00 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* PHCON1 values */ 229*4882a593Smuzhiyun #define ENC_PHCON1_PDPXMD 0x0100 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* PHSTAT1 values */ 232*4882a593Smuzhiyun #define ENC_PHSTAT1_LLSTAT 0x0004 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* PHSTAT2 values */ 235*4882a593Smuzhiyun #define ENC_PHSTAT2_LSTAT 0x0400 236*4882a593Smuzhiyun #define ENC_PHSTAT2_DPXSTAT 0x0200 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun #endif 239