1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2020 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DWC_ETH_QOS_H 7*4882a593Smuzhiyun #define _DWC_ETH_QOS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/gpio.h> 10*4882a593Smuzhiyun #include <reset.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 13*4882a593Smuzhiyun #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 14*4882a593Smuzhiyun #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 17*4882a593Smuzhiyun #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 18*4882a593Smuzhiyun #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct eqos_config { 21*4882a593Smuzhiyun bool reg_access_always_ok; 22*4882a593Smuzhiyun int mdio_wait; 23*4882a593Smuzhiyun int swr_wait; 24*4882a593Smuzhiyun int config_mac; 25*4882a593Smuzhiyun int config_mac_mdio; 26*4882a593Smuzhiyun struct eqos_ops *ops; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct eqos_ops { 30*4882a593Smuzhiyun void (*eqos_inval_desc)(void *desc); 31*4882a593Smuzhiyun void (*eqos_flush_desc)(void *desc); 32*4882a593Smuzhiyun void (*eqos_inval_buffer)(void *buf, size_t size); 33*4882a593Smuzhiyun void (*eqos_flush_buffer)(void *buf, size_t size); 34*4882a593Smuzhiyun int (*eqos_probe_resources)(struct udevice *dev); 35*4882a593Smuzhiyun int (*eqos_remove_resources)(struct udevice *dev); 36*4882a593Smuzhiyun int (*eqos_stop_resets)(struct udevice *dev); 37*4882a593Smuzhiyun int (*eqos_start_resets)(struct udevice *dev); 38*4882a593Smuzhiyun void (*eqos_stop_clks)(struct udevice *dev); 39*4882a593Smuzhiyun int (*eqos_start_clks)(struct udevice *dev); 40*4882a593Smuzhiyun int (*eqos_calibrate_pads)(struct udevice *dev); 41*4882a593Smuzhiyun int (*eqos_disable_calibration)(struct udevice *dev); 42*4882a593Smuzhiyun int (*eqos_set_tx_clk_speed)(struct udevice *dev); 43*4882a593Smuzhiyun ulong (*eqos_get_tick_clk_rate)(struct udevice *dev); 44*4882a593Smuzhiyun phy_interface_t (*eqos_get_interface)(struct udevice *dev); 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct eqos_priv { 48*4882a593Smuzhiyun struct udevice *dev; 49*4882a593Smuzhiyun const struct eqos_config *config; 50*4882a593Smuzhiyun fdt_addr_t regs; 51*4882a593Smuzhiyun struct eqos_mac_regs *mac_regs; 52*4882a593Smuzhiyun struct eqos_mtl_regs *mtl_regs; 53*4882a593Smuzhiyun struct eqos_dma_regs *dma_regs; 54*4882a593Smuzhiyun struct eqos_tegra186_regs *tegra186_regs; 55*4882a593Smuzhiyun struct reset_ctl reset_ctl; 56*4882a593Smuzhiyun struct gpio_desc phy_reset_gpio; 57*4882a593Smuzhiyun u32 reset_delays[3]; 58*4882a593Smuzhiyun struct clk clk_master_bus; 59*4882a593Smuzhiyun struct clk clk_rx; 60*4882a593Smuzhiyun struct clk clk_ptp_ref; 61*4882a593Smuzhiyun struct clk clk_tx; 62*4882a593Smuzhiyun struct clk clk_ck; 63*4882a593Smuzhiyun struct clk clk_slave_bus; 64*4882a593Smuzhiyun struct mii_dev *mii; 65*4882a593Smuzhiyun struct phy_device *phy; 66*4882a593Smuzhiyun int phyaddr; 67*4882a593Smuzhiyun u32 max_speed; 68*4882a593Smuzhiyun void *descs; 69*4882a593Smuzhiyun struct eqos_desc *tx_descs; 70*4882a593Smuzhiyun struct eqos_desc *rx_descs; 71*4882a593Smuzhiyun int tx_desc_idx, rx_desc_idx; 72*4882a593Smuzhiyun void *tx_dma_buf; 73*4882a593Smuzhiyun void *rx_dma_buf; 74*4882a593Smuzhiyun void *rx_pkt; 75*4882a593Smuzhiyun bool started; 76*4882a593Smuzhiyun bool reg_access_ok; 77*4882a593Smuzhiyun bool mii_reseted; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun int eqos_init(struct udevice *dev); 81*4882a593Smuzhiyun void eqos_enable(struct udevice *dev); 82*4882a593Smuzhiyun int eqos_probe(struct udevice *dev); 83*4882a593Smuzhiyun void eqos_stop(struct udevice *dev); 84*4882a593Smuzhiyun int eqos_send(struct udevice *dev, void *packet, int length); 85*4882a593Smuzhiyun int eqos_recv(struct udevice *dev, int flags, uchar **packetp); 86*4882a593Smuzhiyun int eqos_free_pkt(struct udevice *dev, uchar *packet, int length); 87*4882a593Smuzhiyun int eqos_write_hwaddr(struct udevice *dev); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun extern struct eqos_ops eqos_rockchip_ops; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif 92