1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AX88796L(NE2000) support 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DRIVERS_AX88796L_H__ 10*4882a593Smuzhiyun #define __DRIVERS_AX88796L_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define DP_DATA (0x10 << 1) 13*4882a593Smuzhiyun #define START_PG 0x40 /* First page of TX buffer */ 14*4882a593Smuzhiyun #define START_PG2 0x48 15*4882a593Smuzhiyun #define STOP_PG 0x80 /* Last page +1 of RX ring */ 16*4882a593Smuzhiyun #define TX_PAGES 12 17*4882a593Smuzhiyun #define RX_START (START_PG+TX_PAGES) 18*4882a593Smuzhiyun #define RX_END STOP_PG 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE 21*4882a593Smuzhiyun #define AX88796L_BYTE_ACCESS 0x00001000 22*4882a593Smuzhiyun #define AX88796L_OFFSET 0x00000400 23*4882a593Smuzhiyun #define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ 24*4882a593Smuzhiyun AX88796L_BYTE_ACCESS + AX88796L_OFFSET 25*4882a593Smuzhiyun #define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) 26*4882a593Smuzhiyun #define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) 29*4882a593Smuzhiyun #define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define EECS_HIGH (AX88796L_MEMR |= 0x10) 32*4882a593Smuzhiyun #define EECS_LOW (AX88796L_MEMR &= 0xef) 33*4882a593Smuzhiyun #define EECLK_HIGH (AX88796L_MEMR |= 0x80) 34*4882a593Smuzhiyun #define EECLK_LOW (AX88796L_MEMR &= 0x7f) 35*4882a593Smuzhiyun #define EEDI_HIGH (AX88796L_MEMR |= 0x20) 36*4882a593Smuzhiyun #define EEDI_LOW (AX88796L_MEMR &= 0xdf) 37*4882a593Smuzhiyun #define EEDO ((AX88796L_MEMR & 0x40)>>6) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PAGE0_SET (AX88796L_CR &= 0x3f) 40*4882a593Smuzhiyun #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define BIT_DUMMY 0 43*4882a593Smuzhiyun #define MAC_EEP_READ 1 44*4882a593Smuzhiyun #define MAC_EEP_WRITE 2 45*4882a593Smuzhiyun #define MAC_EEP_ERACE 3 46*4882a593Smuzhiyun #define MAC_EEP_EWEN 4 47*4882a593Smuzhiyun #define MAC_EEP_EWDS 5 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* R7780MP Specific code */ 50*4882a593Smuzhiyun #if defined(CONFIG_R7780MP) 51*4882a593Smuzhiyun #define ISA_OFFSET 0x1400 52*4882a593Smuzhiyun #define DP_IN(_b_, _o_, _d_) (_d_) = \ 53*4882a593Smuzhiyun *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) 54*4882a593Smuzhiyun #define DP_OUT(_b_, _o_, _d_) \ 55*4882a593Smuzhiyun *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) 56*4882a593Smuzhiyun #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) 57*4882a593Smuzhiyun #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) 58*4882a593Smuzhiyun #else 59*4882a593Smuzhiyun /* Please change for your target boards */ 60*4882a593Smuzhiyun #define ISA_OFFSET 0x0000 61*4882a593Smuzhiyun #define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) 62*4882a593Smuzhiyun #define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) 63*4882a593Smuzhiyun #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) 64*4882a593Smuzhiyun #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __DRIVERS_AX88796L_H__ */ 68