1*4882a593Smuzhiyun struct stm32_flash_regs { 2*4882a593Smuzhiyun u32 acr; 3*4882a593Smuzhiyun u32 key; 4*4882a593Smuzhiyun u32 optkeyr; 5*4882a593Smuzhiyun u32 sr; 6*4882a593Smuzhiyun u32 cr; 7*4882a593Smuzhiyun u32 optcr; 8*4882a593Smuzhiyun u32 optcr1; 9*4882a593Smuzhiyun }; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define STM32_FLASH_KEY1 0x45670123 12*4882a593Smuzhiyun #define STM32_FLASH_KEY2 0xCDEF89AB 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define STM32_FLASH_SR_BSY (1 << 16) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define STM32_FLASH_CR_PG (1 << 0) 17*4882a593Smuzhiyun #define STM32_FLASH_CR_SER (1 << 1) 18*4882a593Smuzhiyun #define STM32_FLASH_CR_STRT (1 << 16) 19*4882a593Smuzhiyun #define STM32_FLASH_CR_LOCK (1 << 31) 20*4882a593Smuzhiyun #define STM32_FLASH_CR_SNB_OFFSET 3 21*4882a593Smuzhiyun #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Flash ACR: Access control register */ 24*4882a593Smuzhiyun #define FLASH_ACR_WS(n) n 25*4882a593Smuzhiyun #define FLASH_ACR_PRFTEN (1 << 8) 26*4882a593Smuzhiyun #define FLASH_ACR_ICEN (1 << 9) 27*4882a593Smuzhiyun #define FLASH_ACR_DCEN (1 << 10) 28