1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Exclude chip names for SPL to save space */ 16 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17 #define INFO_NAME(_name) .name = _name, 18 #else 19 #define INFO_NAME(_name) 20 #endif 21 22 /* Used when the "_ext_id" is two bytes at most */ 23 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24 INFO_NAME(_name) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff, \ 29 ((_ext_id) >> 8) & 0xff, \ 30 (_ext_id) & 0xff, \ 31 }, \ 32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33 .sector_size = (_sector_size), \ 34 .n_sectors = (_n_sectors), \ 35 .page_size = 256, \ 36 .flags = (_flags), 37 38 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39 INFO_NAME(_name) \ 40 .id = { \ 41 ((_jedec_id) >> 16) & 0xff, \ 42 ((_jedec_id) >> 8) & 0xff, \ 43 (_jedec_id) & 0xff, \ 44 ((_ext_id) >> 16) & 0xff, \ 45 ((_ext_id) >> 8) & 0xff, \ 46 (_ext_id) & 0xff, \ 47 }, \ 48 .id_len = 6, \ 49 .sector_size = (_sector_size), \ 50 .n_sectors = (_n_sectors), \ 51 .page_size = 256, \ 52 .flags = (_flags), 53 54 /* NOTE: double check command sets and memory organization when you add 55 * more nor chips. This current list focusses on newer chips, which 56 * have been converging on command sets which including JEDEC ID. 57 * 58 * All newly added entries should describe *hardware* and should use SECT_4K 59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60 * scenarios excluding small sectors there is config option that can be 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. 62 * For historical (and compatibility) reasons (before we got above config) some 63 * old entries may be missing 4K flag. 64 */ 65 const struct flash_info spi_nor_ids[] = { 66 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70 71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 80 #endif 81 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 82 /* EON -- en25xxx */ 83 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 84 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 85 { INFO("en25qh64", 0x1c7017, 0, 64 * 1024, 128, SECT_4K) }, 86 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K) }, 87 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 88 { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 89 { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 90 { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 91 #endif 92 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 93 /* GigaDevice */ 94 { 95 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 96 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 97 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 98 }, 99 { 100 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 101 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 102 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 103 }, 104 { 105 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 106 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 107 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 108 }, 109 { 110 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 111 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 112 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 113 }, 114 { 115 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, 116 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 117 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 118 }, 119 { 120 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, 121 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 122 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 123 }, 124 { INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024, 125 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 126 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 127 SPI_NOR_HAS_TB) 128 }, 129 { 130 INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024, 131 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 132 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 133 }, 134 { 135 INFO("gd55lb01ge", 0xc8671b, 0, 64 * 1024, 2048, 136 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 137 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 138 }, 139 { 140 INFO("gd25b512m", 0xc8471a, 0, 64 * 1024, 1024, 141 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 142 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 143 }, 144 { 145 INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048, 146 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 147 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 148 }, 149 /* adding these 3V QSPI flash parts */ 150 {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | 151 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, 152 {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | 153 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 154 {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | 155 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 156 {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | 157 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 158 {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | 159 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 160 {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K | 161 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 162 {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K | 163 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 164 {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K | 165 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 166 {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K | 167 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 168 {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | 169 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 170 {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | 171 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 172 /* adding these 3V OSPI flash parts */ 173 {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | 174 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 175 {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | 176 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 177 {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | 178 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 179 { 180 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, 181 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 182 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 183 }, 184 { 185 INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512, 186 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 187 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 188 }, 189 /* adding these 1.8V QSPI flash parts */ 190 {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | 191 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 192 {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | 193 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 194 {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | 195 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 196 {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | 197 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 198 {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | 199 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 200 {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | 201 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 202 {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | 203 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 204 {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | 205 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 206 {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | 207 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 208 {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | 209 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 210 {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | 211 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 212 {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | 213 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 214 {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | 215 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 216 {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | 217 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 218 {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | 219 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 220 { 221 INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, 222 SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) 223 }, 224 /* adding these 1.8V OSPI flash parts */ 225 {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | 226 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 227 {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K | 228 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 229 {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | 230 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 231 #endif 232 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 233 /* ISSI */ 234 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 235 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 236 { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, 237 { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, 238 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 239 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 240 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 241 SECT_4K | SPI_NOR_DUAL_READ) }, 242 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 243 SECT_4K | SPI_NOR_DUAL_READ) }, 244 { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, 245 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 246 { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, 247 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 248 { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, 249 { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, 250 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 251 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 252 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 253 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 254 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 255 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 256 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, 257 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 258 SPI_NOR_4B_OPCODES) }, 259 { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, 260 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 261 { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, 262 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 263 { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, 264 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 265 #endif 266 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 267 /* Macronix */ 268 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 269 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 270 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 271 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 272 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 273 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 274 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 275 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 276 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, 277 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 278 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 279 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 280 { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | 281 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 282 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 283 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 284 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 285 { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 286 { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 287 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 288 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 289 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 290 { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 291 { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 292 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 293 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 294 { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 295 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 296 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, 297 { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 298 { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 299 { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 300 { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 301 { INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 302 { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 303 { INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 304 { INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 305 { INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 306 { INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 307 { INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 308 { INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 309 { INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 310 { INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 311 { INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 312 { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 313 { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 314 { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 315 #endif 316 317 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 318 /* Micron */ 319 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 320 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 321 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 322 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 323 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 324 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 325 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 326 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 327 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, 328 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 329 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, 330 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, 331 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 332 USE_FSR) }, 333 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 334 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 335 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 336 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 337 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 338 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 339 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 340 { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, 341 #ifdef CONFIG_SPI_FLASH_MT35XU 342 { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, 343 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, 344 #endif /* CONFIG_SPI_FLASH_MT35XU */ 345 { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 346 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 347 #endif 348 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 349 /* Spansion/Cypress -- single (large) sector size only, at least 350 * for the chips listed here (without boot sectors). 351 */ 352 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 353 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 354 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 355 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 356 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 357 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 358 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 359 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 360 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 361 { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 362 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 363 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 364 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 365 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 366 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 367 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 368 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 369 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 370 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 371 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 372 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 373 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 374 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 375 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 376 #endif 377 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 378 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 379 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 380 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 381 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 382 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 383 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 384 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 385 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 386 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 387 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 388 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 389 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 390 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 391 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 392 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 393 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 394 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 395 #endif 396 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 397 /* ST Microelectronics -- newer production may have feature updates */ 398 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 399 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 400 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 401 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 402 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 403 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 404 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 405 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 406 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 407 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 408 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 409 #endif 410 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 411 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 412 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 413 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 414 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 415 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 416 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 417 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 418 { 419 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 420 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 421 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 422 }, 423 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 424 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 425 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 426 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 427 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 428 { 429 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 430 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 431 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 432 }, 433 { 434 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 435 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 436 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 437 }, 438 { 439 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, 440 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 441 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 442 }, 443 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 444 { 445 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 446 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 447 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 448 }, 449 { 450 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 451 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 452 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 453 }, 454 { 455 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 456 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 457 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 458 }, 459 { 460 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 461 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 462 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 463 }, 464 { 465 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 466 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 467 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 468 }, 469 { 470 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, 471 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 472 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 473 }, 474 { 475 INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, 476 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 477 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 478 }, 479 { 480 INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, 481 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 482 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 483 }, 484 { 485 INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024, 486 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 487 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 488 }, 489 { 490 INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024, 491 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 492 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 493 }, 494 { 495 INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, 496 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 497 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 498 }, 499 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 500 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 501 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 502 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 503 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, 504 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 505 SPI_NOR_HAS_TB) 506 }, 507 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 508 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 509 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 510 { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 511 #endif 512 #ifdef CONFIG_SPI_FLASH_XMC 513 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 514 { INFO("XM25QH32A", 0x207016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 515 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 516 { INFO("XM25QH64B", 0x206017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 517 { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 518 { INFO("XM25QU64C", 0x204117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 519 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 520 { INFO("XM25QH128B", 0x206018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 521 { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 522 { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 523 { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 524 #endif 525 #ifdef CONFIG_SPI_FLASH_XTX 526 /* XTX Technology (Shenzhen) Limited */ 527 { INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 528 { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 529 { INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 530 { INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 531 { INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 532 #endif 533 #ifdef CONFIG_SPI_FLASH_PUYA 534 /* PUYA Semiconductor (Shanghai) Co., Ltd. */ 535 { INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 536 { INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 537 { INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 538 { INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 539 { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 540 #endif 541 #ifdef CONFIG_SPI_FLASH_FMSH 542 /* FUDAN MICRO (Shanghai) Co., Ltd. */ 543 { INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 544 { INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 545 { INFO("FM25Q256I3", 0xA14019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 546 #endif 547 #ifdef CONFIG_SPI_FLASH_DOSILICON 548 /* Dosilicon Co., Ltd. */ 549 { INFO("FM25Q64A", 0xf83217, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 550 { INFO("FM25M4AA", 0xf84218, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 551 { INFO("FM25M64C", 0xf84317, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 552 #endif 553 #ifdef CONFIG_SPI_FLASH_BOYA 554 /* Boya Microelectronics Co., Ltd. */ 555 { INFO("BY25Q256FSEIG", 0x684919, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 556 #endif 557 #ifdef CONFIG_SPI_FLASH_NORMEM 558 /* NORMEM Microelectronics Co., Ltd. */ 559 { INFO("NM25Q128EVB", 0x522118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 560 #endif 561 { }, 562 }; 563