1 /*
2 * Atmel DataFlash probing
3 *
4 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
5 * Haikun Wang (haikun.wang@freescale.com)
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <spi.h>
15 #include <spi_flash.h>
16 #include <div64.h>
17 #include <linux/err.h>
18 #include <linux/math64.h>
19
20 #include "sf_internal.h"
21
22 #define CMD_READ_ID 0x9f
23 /* reads can bypass the buffers */
24 #define OP_READ_CONTINUOUS 0xE8
25 #define OP_READ_PAGE 0xD2
26
27 /* group B requests can run even while status reports "busy" */
28 #define OP_READ_STATUS 0xD7 /* group B */
29
30 /* move data between host and buffer */
31 #define OP_READ_BUFFER1 0xD4 /* group B */
32 #define OP_READ_BUFFER2 0xD6 /* group B */
33 #define OP_WRITE_BUFFER1 0x84 /* group B */
34 #define OP_WRITE_BUFFER2 0x87 /* group B */
35
36 /* erasing flash */
37 #define OP_ERASE_PAGE 0x81
38 #define OP_ERASE_BLOCK 0x50
39
40 /* move data between buffer and flash */
41 #define OP_TRANSFER_BUF1 0x53
42 #define OP_TRANSFER_BUF2 0x55
43 #define OP_MREAD_BUFFER1 0xD4
44 #define OP_MREAD_BUFFER2 0xD6
45 #define OP_MWERASE_BUFFER1 0x83
46 #define OP_MWERASE_BUFFER2 0x86
47 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
48 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
49
50 /* write to buffer, then write-erase to flash */
51 #define OP_PROGRAM_VIA_BUF1 0x82
52 #define OP_PROGRAM_VIA_BUF2 0x85
53
54 /* compare buffer to flash */
55 #define OP_COMPARE_BUF1 0x60
56 #define OP_COMPARE_BUF2 0x61
57
58 /* read flash to buffer, then write-erase to flash */
59 #define OP_REWRITE_VIA_BUF1 0x58
60 #define OP_REWRITE_VIA_BUF2 0x59
61
62 /*
63 * newer chips report JEDEC manufacturer and device IDs; chip
64 * serial number and OTP bits; and per-sector writeprotect.
65 */
66 #define OP_READ_ID 0x9F
67 #define OP_READ_SECURITY 0x77
68 #define OP_WRITE_SECURITY_REVC 0x9A
69 #define OP_WRITE_SECURITY 0x9B /* revision D */
70
71 struct dataflash {
72 uint8_t command[16];
73 unsigned short page_offset; /* offset in flash address */
74 };
75
76 /* Return the status of the DataFlash device */
dataflash_status(struct spi_slave * spi)77 static inline int dataflash_status(struct spi_slave *spi)
78 {
79 int ret;
80 u8 opcode = OP_READ_STATUS;
81 u8 status;
82
83 /*
84 * NOTE: at45db321c over 25 MHz wants to write
85 * a dummy byte after the opcode...
86 */
87 ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
88 return ret ? -EIO : status;
89 }
90
91 /*
92 * Poll the DataFlash device until it is READY.
93 * This usually takes 5-20 msec or so; more for sector erase.
94 * ready: return > 0
95 */
dataflash_waitready(struct spi_slave * spi)96 static int dataflash_waitready(struct spi_slave *spi)
97 {
98 int status;
99 int timeout = 2 * CONFIG_SYS_HZ;
100 int timebase;
101
102 timebase = get_timer(0);
103 do {
104 status = dataflash_status(spi);
105 if (status < 0)
106 status = 0;
107
108 if (status & (1 << 7)) /* RDY/nBSY */
109 return status;
110
111 mdelay(3);
112 } while (get_timer(timebase) < timeout);
113
114 return -ETIME;
115 }
116
117 /* Erase pages of flash */
spi_dataflash_erase(struct udevice * dev,u32 offset,size_t len)118 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
119 {
120 struct dataflash *dataflash;
121 struct spi_flash *spi_flash;
122 struct spi_slave *spi;
123 unsigned blocksize;
124 uint8_t *command;
125 uint32_t rem;
126 int status;
127
128 dataflash = dev_get_priv(dev);
129 spi_flash = dev_get_uclass_priv(dev);
130 spi = spi_flash->spi;
131
132 blocksize = spi_flash->page_size << 3;
133
134 memset(dataflash->command, 0 , sizeof(dataflash->command));
135 command = dataflash->command;
136
137 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
138
139 div_u64_rem(len, spi_flash->page_size, &rem);
140 if (rem) {
141 printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
142 dev->name, len, spi_flash->page_size);
143 return -EINVAL;
144 }
145 div_u64_rem(offset, spi_flash->page_size, &rem);
146 if (rem) {
147 printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
148 dev->name, offset, spi_flash->page_size);
149 return -EINVAL;
150 }
151
152 status = spi_claim_bus(spi);
153 if (status) {
154 debug("dataflash: unable to claim SPI bus\n");
155 return status;
156 }
157
158 while (len > 0) {
159 unsigned int pageaddr;
160 int do_block;
161 /*
162 * Calculate flash page address; use block erase (for speed) if
163 * we're at a block boundary and need to erase the whole block.
164 */
165 pageaddr = div_u64(offset, spi_flash->page_size);
166 do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
167 pageaddr = pageaddr << dataflash->page_offset;
168
169 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
170 command[1] = (uint8_t)(pageaddr >> 16);
171 command[2] = (uint8_t)(pageaddr >> 8);
172 command[3] = 0;
173
174 debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
175 dev->name, do_block ? "block" : "page",
176 command[0], command[1], command[2], command[3],
177 pageaddr);
178
179 status = spi_write_then_read(spi, command, 4, NULL, NULL, 0);
180 if (status < 0) {
181 debug("%s: erase send command error!\n", dev->name);
182 return -EIO;
183 }
184
185 status = dataflash_waitready(spi);
186 if (status < 0) {
187 debug("%s: erase waitready error!\n", dev->name);
188 return status;
189 }
190
191 if (do_block) {
192 offset += blocksize;
193 len -= blocksize;
194 } else {
195 offset += spi_flash->page_size;
196 len -= spi_flash->page_size;
197 }
198 }
199
200 spi_release_bus(spi);
201
202 return 0;
203 }
204
205 /*
206 * Read from the DataFlash device.
207 * offset : Start offset in flash device
208 * len : Amount to read
209 * buf : Buffer containing the data
210 */
spi_dataflash_read(struct udevice * dev,u32 offset,size_t len,void * buf)211 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
212 void *buf)
213 {
214 struct dataflash *dataflash;
215 struct spi_flash *spi_flash;
216 struct spi_slave *spi;
217 unsigned int addr;
218 uint8_t *command;
219 int status;
220
221 dataflash = dev_get_priv(dev);
222 spi_flash = dev_get_uclass_priv(dev);
223 spi = spi_flash->spi;
224
225 memset(dataflash->command, 0 , sizeof(dataflash->command));
226 command = dataflash->command;
227
228 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
229 debug("READ: (%x) %x %x %x\n",
230 command[0], command[1], command[2], command[3]);
231
232 /* Calculate flash page/byte address */
233 addr = (((unsigned)offset / spi_flash->page_size)
234 << dataflash->page_offset)
235 + ((unsigned)offset % spi_flash->page_size);
236
237 status = spi_claim_bus(spi);
238 if (status) {
239 debug("dataflash: unable to claim SPI bus\n");
240 return status;
241 }
242
243 /*
244 * Continuous read, max clock = f(car) which may be less than
245 * the peak rate available. Some chips support commands with
246 * fewer "don't care" bytes. Both buffers stay unchanged.
247 */
248 command[0] = OP_READ_CONTINUOUS;
249 command[1] = (uint8_t)(addr >> 16);
250 command[2] = (uint8_t)(addr >> 8);
251 command[3] = (uint8_t)(addr >> 0);
252
253 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
254 status = spi_write_then_read(spi, command, 8, NULL, buf, len);
255
256 spi_release_bus(spi);
257
258 return status;
259 }
260
261 /*
262 * Write to the DataFlash device.
263 * offset : Start offset in flash device
264 * len : Amount to write
265 * buf : Buffer containing the data
266 */
spi_dataflash_write(struct udevice * dev,u32 offset,size_t len,const void * buf)267 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
268 const void *buf)
269 {
270 struct dataflash *dataflash;
271 struct spi_flash *spi_flash;
272 struct spi_slave *spi;
273 uint8_t *command;
274 unsigned int pageaddr, addr, to, writelen;
275 size_t remaining = len;
276 u_char *writebuf = (u_char *)buf;
277 int status = -EINVAL;
278
279 dataflash = dev_get_priv(dev);
280 spi_flash = dev_get_uclass_priv(dev);
281 spi = spi_flash->spi;
282
283 memset(dataflash->command, 0 , sizeof(dataflash->command));
284 command = dataflash->command;
285
286 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
287
288 pageaddr = ((unsigned)offset / spi_flash->page_size);
289 to = ((unsigned)offset % spi_flash->page_size);
290 if (to + len > spi_flash->page_size)
291 writelen = spi_flash->page_size - to;
292 else
293 writelen = len;
294
295 status = spi_claim_bus(spi);
296 if (status) {
297 debug("dataflash: unable to claim SPI bus\n");
298 return status;
299 }
300
301 while (remaining > 0) {
302 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
303
304 /*
305 * REVISIT:
306 * (a) each page in a sector must be rewritten at least
307 * once every 10K sibling erase/program operations.
308 * (b) for pages that are already erased, we could
309 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
310 * (c) WRITE to buffer could be done while waiting for
311 * a previous MWRITE/MWERASE to complete ...
312 * (d) error handling here seems to be mostly missing.
313 *
314 * Two persistent bits per page, plus a per-sector counter,
315 * could support (a) and (b) ... we might consider using
316 * the second half of sector zero, which is just one block,
317 * to track that state. (On AT91, that sector should also
318 * support boot-from-DataFlash.)
319 */
320
321 addr = pageaddr << dataflash->page_offset;
322
323 /* (1) Maybe transfer partial page to Buffer1 */
324 if (writelen != spi_flash->page_size) {
325 command[0] = OP_TRANSFER_BUF1;
326 command[1] = (addr & 0x00FF0000) >> 16;
327 command[2] = (addr & 0x0000FF00) >> 8;
328 command[3] = 0;
329
330 debug("TRANSFER: (%x) %x %x %x\n",
331 command[0], command[1], command[2], command[3]);
332
333 status = spi_write_then_read(spi, command, 4,
334 NULL, NULL, 0);
335 if (status < 0) {
336 debug("%s: write(<pagesize) command error!\n",
337 dev->name);
338 return -EIO;
339 }
340
341 status = dataflash_waitready(spi);
342 if (status < 0) {
343 debug("%s: write(<pagesize) waitready error!\n",
344 dev->name);
345 return status;
346 }
347 }
348
349 /* (2) Program full page via Buffer1 */
350 addr += to;
351 command[0] = OP_PROGRAM_VIA_BUF1;
352 command[1] = (addr & 0x00FF0000) >> 16;
353 command[2] = (addr & 0x0000FF00) >> 8;
354 command[3] = (addr & 0x000000FF);
355
356 debug("PROGRAM: (%x) %x %x %x\n",
357 command[0], command[1], command[2], command[3]);
358
359 status = spi_write_then_read(spi, command, 4,
360 writebuf, NULL, writelen);
361 if (status < 0) {
362 debug("%s: write send command error!\n", dev->name);
363 return -EIO;
364 }
365
366 status = dataflash_waitready(spi);
367 if (status < 0) {
368 debug("%s: write waitready error!\n", dev->name);
369 return status;
370 }
371
372 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
373 /* (3) Compare to Buffer1 */
374 addr = pageaddr << dataflash->page_offset;
375 command[0] = OP_COMPARE_BUF1;
376 command[1] = (addr & 0x00FF0000) >> 16;
377 command[2] = (addr & 0x0000FF00) >> 8;
378 command[3] = 0;
379
380 debug("COMPARE: (%x) %x %x %x\n",
381 command[0], command[1], command[2], command[3]);
382
383 status = spi_write_then_read(spi, command, 4,
384 writebuf, NULL, writelen);
385 if (status < 0) {
386 debug("%s: write(compare) send command error!\n",
387 dev->name);
388 return -EIO;
389 }
390
391 status = dataflash_waitready(spi);
392
393 /* Check result of the compare operation */
394 if (status & (1 << 6)) {
395 printf("dataflash: write compare page %u, err %d\n",
396 pageaddr, status);
397 remaining = 0;
398 status = -EIO;
399 break;
400 } else {
401 status = 0;
402 }
403
404 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
405 remaining = remaining - writelen;
406 pageaddr++;
407 to = 0;
408 writebuf += writelen;
409
410 if (remaining > spi_flash->page_size)
411 writelen = spi_flash->page_size;
412 else
413 writelen = remaining;
414 }
415
416 spi_release_bus(spi);
417
418 return 0;
419 }
420
add_dataflash(struct udevice * dev,char * name,int nr_pages,int pagesize,int pageoffset,char revision)421 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
422 int pagesize, int pageoffset, char revision)
423 {
424 struct spi_flash *spi_flash;
425 struct dataflash *dataflash;
426
427 dataflash = dev_get_priv(dev);
428 spi_flash = dev_get_uclass_priv(dev);
429
430 dataflash->page_offset = pageoffset;
431
432 spi_flash->name = name;
433 spi_flash->page_size = pagesize;
434 spi_flash->size = nr_pages * pagesize;
435 spi_flash->erase_size = pagesize;
436
437 #ifndef CONFIG_SPL_BUILD
438 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
439 print_size(spi_flash->page_size, ", erase size ");
440 print_size(spi_flash->erase_size, ", total ");
441 print_size(spi_flash->size, "");
442 printf(", revision %c", revision);
443 puts("\n");
444 #endif
445
446 return 0;
447 }
448
449 struct data_flash_info {
450 char *name;
451
452 /*
453 * JEDEC id has a high byte of zero plus three data bytes:
454 * the manufacturer id, then a two byte device id.
455 */
456 uint32_t jedec_id;
457
458 /* The size listed here is what works with OP_ERASE_PAGE. */
459 unsigned nr_pages;
460 uint16_t pagesize;
461 uint16_t pageoffset;
462
463 uint16_t flags;
464 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
465 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
466 };
467
468 static struct data_flash_info dataflash_data[] = {
469 /*
470 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
471 * one with IS_POW2PS and the other without. The entry with the
472 * non-2^N byte page size can't name exact chip revisions without
473 * losing backwards compatibility for cmdlinepart.
474 *
475 * Those two entries have different name spelling format in order to
476 * show their difference obviously.
477 * The upper case refer to the chip isn't in normal 2^N bytes page-size
478 * mode.
479 * The lower case refer to the chip is in normal 2^N bytes page-size
480 * mode.
481 *
482 * These newer chips also support 128-byte security registers (with
483 * 64 bytes one-time-programmable) and software write-protection.
484 */
485 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
486 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
487
488 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
489 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
490
491 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
492 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
493
494 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
495 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
496
497 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
498 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
499
500 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
501
502 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
503 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
504
505 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
506 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
507 };
508
jedec_probe(struct spi_slave * spi)509 static struct data_flash_info *jedec_probe(struct spi_slave *spi)
510 {
511 int tmp;
512 uint8_t id[5];
513 uint32_t jedec;
514 struct data_flash_info *info;
515 u8 opcode = CMD_READ_ID;
516 int status;
517
518 /*
519 * JEDEC also defines an optional "extended device information"
520 * string for after vendor-specific data, after the three bytes
521 * we use here. Supporting some chips might require using it.
522 *
523 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
524 * That's not an error; only rev C and newer chips handle it, and
525 * only Atmel sells these chips.
526 */
527 tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, sizeof(id));
528 if (tmp < 0) {
529 printf("dataflash: error %d reading JEDEC ID\n", tmp);
530 return ERR_PTR(tmp);
531 }
532 if (id[0] != 0x1f)
533 return NULL;
534
535 jedec = id[0];
536 jedec = jedec << 8;
537 jedec |= id[1];
538 jedec = jedec << 8;
539 jedec |= id[2];
540
541 for (tmp = 0, info = dataflash_data;
542 tmp < ARRAY_SIZE(dataflash_data);
543 tmp++, info++) {
544 if (info->jedec_id == jedec) {
545 if (info->flags & SUP_POW2PS) {
546 status = dataflash_status(spi);
547 if (status < 0) {
548 debug("dataflash: status error %d\n",
549 status);
550 return NULL;
551 }
552 if (status & 0x1) {
553 if (info->flags & IS_POW2PS)
554 return info;
555 } else {
556 if (!(info->flags & IS_POW2PS))
557 return info;
558 }
559 } else {
560 return info;
561 }
562 }
563 }
564
565 /*
566 * Treat other chips as errors ... we won't know the right page
567 * size (it might be binary) even when we can tell which density
568 * class is involved (legacy chip id scheme).
569 */
570 printf("dataflash: JEDEC id %06x not handled\n", jedec);
571 return ERR_PTR(-ENODEV);
572 }
573
574 /*
575 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
576 * or else the ID code embedded in the status bits:
577 *
578 * Device Density ID code #Pages PageSize Offset
579 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
580 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
581 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
582 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
583 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
584 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
585 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
586 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
587 */
spi_dataflash_probe(struct udevice * dev)588 static int spi_dataflash_probe(struct udevice *dev)
589 {
590 struct spi_slave *spi = dev_get_parent_priv(dev);
591 struct spi_flash *spi_flash;
592 struct data_flash_info *info;
593 int status;
594
595 spi_flash = dev_get_uclass_priv(dev);
596 spi_flash->spi = spi;
597 spi_flash->dev = dev;
598
599 status = spi_claim_bus(spi);
600 if (status)
601 return status;
602
603 /*
604 * Try to detect dataflash by JEDEC ID.
605 * If it succeeds we know we have either a C or D part.
606 * D will support power of 2 pagesize option.
607 * Both support the security register, though with different
608 * write procedures.
609 */
610 info = jedec_probe(spi);
611 if (IS_ERR(info))
612 goto err_jedec_probe;
613 if (info != NULL) {
614 status = add_dataflash(dev, info->name, info->nr_pages,
615 info->pagesize, info->pageoffset,
616 (info->flags & SUP_POW2PS) ? 'd' : 'c');
617 if (status < 0)
618 goto err_status;
619 }
620
621 /*
622 * Older chips support only legacy commands, identifing
623 * capacity using bits in the status byte.
624 */
625 status = dataflash_status(spi);
626 if (status <= 0 || status == 0xff) {
627 printf("dataflash: read status error %d\n", status);
628 if (status == 0 || status == 0xff)
629 status = -ENODEV;
630 goto err_jedec_probe;
631 }
632
633 /*
634 * if there's a device there, assume it's dataflash.
635 * board setup should have set spi->max_speed_max to
636 * match f(car) for continuous reads, mode 0 or 3.
637 */
638 switch (status & 0x3c) {
639 case 0x0c: /* 0 0 1 1 x x */
640 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
641 break;
642 case 0x14: /* 0 1 0 1 x x */
643 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
644 break;
645 case 0x1c: /* 0 1 1 1 x x */
646 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
647 break;
648 case 0x24: /* 1 0 0 1 x x */
649 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
650 break;
651 case 0x2c: /* 1 0 1 1 x x */
652 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
653 break;
654 case 0x34: /* 1 1 0 1 x x */
655 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
656 break;
657 case 0x38: /* 1 1 1 x x x */
658 case 0x3c:
659 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
660 break;
661 /* obsolete AT45DB1282 not (yet?) supported */
662 default:
663 printf("dataflash: unsupported device (%x)\n", status & 0x3c);
664 status = -ENODEV;
665 goto err_status;
666 }
667
668 return status;
669
670 err_status:
671 spi_free_slave(spi);
672 err_jedec_probe:
673 spi_release_bus(spi);
674 return status;
675 }
676
677 static const struct dm_spi_flash_ops spi_dataflash_ops = {
678 .read = spi_dataflash_read,
679 .write = spi_dataflash_write,
680 .erase = spi_dataflash_erase,
681 };
682
683 static const struct udevice_id spi_dataflash_ids[] = {
684 { .compatible = "atmel,at45", },
685 { .compatible = "atmel,dataflash", },
686 { }
687 };
688
689 U_BOOT_DRIVER(spi_dataflash) = {
690 .name = "spi_dataflash",
691 .id = UCLASS_SPI_FLASH,
692 .of_match = spi_dataflash_ids,
693 .probe = spi_dataflash_probe,
694 .priv_auto_alloc_size = sizeof(struct dataflash),
695 .ops = &spi_dataflash_ops,
696 };
697