1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * linux/drivers/mtd/onenand/onenand_base.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2005-2007 Samsung Electronics
5*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Credits:
8*4882a593Smuzhiyun * Adrian Hunter <ext-adrian.hunter@nokia.com>:
9*4882a593Smuzhiyun * auto-placement support, read-while load support, various fixes
10*4882a593Smuzhiyun * Copyright (C) Nokia Corporation, 2007
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Rohit Hagargundgi <h.rohit at samsung.com>,
13*4882a593Smuzhiyun * Amul Kumar Saha <amul.saha@samsung.com>:
14*4882a593Smuzhiyun * Flex-OneNAND support
15*4882a593Smuzhiyun * Copyright (C) Samsung Electronics, 2009
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
18*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
19*4882a593Smuzhiyun * published by the Free Software Foundation.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <common.h>
23*4882a593Smuzhiyun #include <watchdog.h>
24*4882a593Smuzhiyun #include <linux/compat.h>
25*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
26*4882a593Smuzhiyun #include "linux/mtd/flashchip.h"
27*4882a593Smuzhiyun #include <linux/mtd/onenand.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <asm/io.h>
30*4882a593Smuzhiyun #include <linux/errno.h>
31*4882a593Smuzhiyun #include <malloc.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* It should access 16-bit instead of 8-bit */
memcpy_16(void * dst,const void * src,unsigned int len)34*4882a593Smuzhiyun static void *memcpy_16(void *dst, const void *src, unsigned int len)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun void *ret = dst;
37*4882a593Smuzhiyun short *d = dst;
38*4882a593Smuzhiyun const short *s = src;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun len >>= 1;
41*4882a593Smuzhiyun while (len-- > 0)
42*4882a593Smuzhiyun *d++ = *s++;
43*4882a593Smuzhiyun return ret;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /**
47*4882a593Smuzhiyun * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
48*4882a593Smuzhiyun * For now, we expose only 64 out of 80 ecc bytes
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun static struct nand_ecclayout onenand_oob_128 = {
51*4882a593Smuzhiyun .eccbytes = 64,
52*4882a593Smuzhiyun .eccpos = {
53*4882a593Smuzhiyun 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
54*4882a593Smuzhiyun 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
55*4882a593Smuzhiyun 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
56*4882a593Smuzhiyun 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
57*4882a593Smuzhiyun 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
58*4882a593Smuzhiyun 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
59*4882a593Smuzhiyun 102, 103, 104, 105
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun .oobfree = {
62*4882a593Smuzhiyun {2, 4}, {18, 4}, {34, 4}, {50, 4},
63*4882a593Smuzhiyun {66, 4}, {82, 4}, {98, 4}, {114, 4}
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /**
68*4882a593Smuzhiyun * onenand_oob_64 - oob info for large (2KB) page
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun static struct nand_ecclayout onenand_oob_64 = {
71*4882a593Smuzhiyun .eccbytes = 20,
72*4882a593Smuzhiyun .eccpos = {
73*4882a593Smuzhiyun 8, 9, 10, 11, 12,
74*4882a593Smuzhiyun 24, 25, 26, 27, 28,
75*4882a593Smuzhiyun 40, 41, 42, 43, 44,
76*4882a593Smuzhiyun 56, 57, 58, 59, 60,
77*4882a593Smuzhiyun },
78*4882a593Smuzhiyun .oobfree = {
79*4882a593Smuzhiyun {2, 3}, {14, 2}, {18, 3}, {30, 2},
80*4882a593Smuzhiyun {34, 3}, {46, 2}, {50, 3}, {62, 2}
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /**
85*4882a593Smuzhiyun * onenand_oob_32 - oob info for middle (1KB) page
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun static struct nand_ecclayout onenand_oob_32 = {
88*4882a593Smuzhiyun .eccbytes = 10,
89*4882a593Smuzhiyun .eccpos = {
90*4882a593Smuzhiyun 8, 9, 10, 11, 12,
91*4882a593Smuzhiyun 24, 25, 26, 27, 28,
92*4882a593Smuzhiyun },
93*4882a593Smuzhiyun .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * Warning! This array is used with the memcpy_16() function, thus
98*4882a593Smuzhiyun * it must be aligned to 2 bytes. GCC can make this array unaligned
99*4882a593Smuzhiyun * as the array is made of unsigned char, which memcpy16() doesn't
100*4882a593Smuzhiyun * like and will cause unaligned access.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun static const unsigned char __aligned(2) ffchars[] = {
103*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
104*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
105*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
106*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
107*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
108*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
109*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
110*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
111*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
112*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
113*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
114*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
115*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
116*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
117*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
118*4882a593Smuzhiyun 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /**
122*4882a593Smuzhiyun * onenand_readw - [OneNAND Interface] Read OneNAND register
123*4882a593Smuzhiyun * @param addr address to read
124*4882a593Smuzhiyun *
125*4882a593Smuzhiyun * Read OneNAND register
126*4882a593Smuzhiyun */
onenand_readw(void __iomem * addr)127*4882a593Smuzhiyun static unsigned short onenand_readw(void __iomem * addr)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun return readw(addr);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /**
133*4882a593Smuzhiyun * onenand_writew - [OneNAND Interface] Write OneNAND register with value
134*4882a593Smuzhiyun * @param value value to write
135*4882a593Smuzhiyun * @param addr address to write
136*4882a593Smuzhiyun *
137*4882a593Smuzhiyun * Write OneNAND register with value
138*4882a593Smuzhiyun */
onenand_writew(unsigned short value,void __iomem * addr)139*4882a593Smuzhiyun static void onenand_writew(unsigned short value, void __iomem * addr)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun writew(value, addr);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /**
145*4882a593Smuzhiyun * onenand_block_address - [DEFAULT] Get block address
146*4882a593Smuzhiyun * @param device the device id
147*4882a593Smuzhiyun * @param block the block
148*4882a593Smuzhiyun * @return translated block address if DDP, otherwise same
149*4882a593Smuzhiyun *
150*4882a593Smuzhiyun * Setup Start Address 1 Register (F100h)
151*4882a593Smuzhiyun */
onenand_block_address(struct onenand_chip * this,int block)152*4882a593Smuzhiyun static int onenand_block_address(struct onenand_chip *this, int block)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun /* Device Flash Core select, NAND Flash Block Address */
155*4882a593Smuzhiyun if (block & this->density_mask)
156*4882a593Smuzhiyun return ONENAND_DDP_CHIP1 | (block ^ this->density_mask);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return block;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /**
162*4882a593Smuzhiyun * onenand_bufferram_address - [DEFAULT] Get bufferram address
163*4882a593Smuzhiyun * @param device the device id
164*4882a593Smuzhiyun * @param block the block
165*4882a593Smuzhiyun * @return set DBS value if DDP, otherwise 0
166*4882a593Smuzhiyun *
167*4882a593Smuzhiyun * Setup Start Address 2 Register (F101h) for DDP
168*4882a593Smuzhiyun */
onenand_bufferram_address(struct onenand_chip * this,int block)169*4882a593Smuzhiyun static int onenand_bufferram_address(struct onenand_chip *this, int block)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun /* Device BufferRAM Select */
172*4882a593Smuzhiyun if (block & this->density_mask)
173*4882a593Smuzhiyun return ONENAND_DDP_CHIP1;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return ONENAND_DDP_CHIP0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /**
179*4882a593Smuzhiyun * onenand_page_address - [DEFAULT] Get page address
180*4882a593Smuzhiyun * @param page the page address
181*4882a593Smuzhiyun * @param sector the sector address
182*4882a593Smuzhiyun * @return combined page and sector address
183*4882a593Smuzhiyun *
184*4882a593Smuzhiyun * Setup Start Address 8 Register (F107h)
185*4882a593Smuzhiyun */
onenand_page_address(int page,int sector)186*4882a593Smuzhiyun static int onenand_page_address(int page, int sector)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun /* Flash Page Address, Flash Sector Address */
189*4882a593Smuzhiyun int fpa, fsa;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun fpa = page & ONENAND_FPA_MASK;
192*4882a593Smuzhiyun fsa = sector & ONENAND_FSA_MASK;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return ((fpa << ONENAND_FPA_SHIFT) | fsa);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun /**
198*4882a593Smuzhiyun * onenand_buffer_address - [DEFAULT] Get buffer address
199*4882a593Smuzhiyun * @param dataram1 DataRAM index
200*4882a593Smuzhiyun * @param sectors the sector address
201*4882a593Smuzhiyun * @param count the number of sectors
202*4882a593Smuzhiyun * @return the start buffer value
203*4882a593Smuzhiyun *
204*4882a593Smuzhiyun * Setup Start Buffer Register (F200h)
205*4882a593Smuzhiyun */
onenand_buffer_address(int dataram1,int sectors,int count)206*4882a593Smuzhiyun static int onenand_buffer_address(int dataram1, int sectors, int count)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun int bsa, bsc;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* BufferRAM Sector Address */
211*4882a593Smuzhiyun bsa = sectors & ONENAND_BSA_MASK;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (dataram1)
214*4882a593Smuzhiyun bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
215*4882a593Smuzhiyun else
216*4882a593Smuzhiyun bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* BufferRAM Sector Count */
219*4882a593Smuzhiyun bsc = count & ONENAND_BSC_MASK;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun return ((bsa << ONENAND_BSA_SHIFT) | bsc);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /**
225*4882a593Smuzhiyun * flexonenand_block - Return block number for flash address
226*4882a593Smuzhiyun * @param this - OneNAND device structure
227*4882a593Smuzhiyun * @param addr - Address for which block number is needed
228*4882a593Smuzhiyun */
flexonenand_block(struct onenand_chip * this,loff_t addr)229*4882a593Smuzhiyun static unsigned int flexonenand_block(struct onenand_chip *this, loff_t addr)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun unsigned int boundary, blk, die = 0;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
234*4882a593Smuzhiyun die = 1;
235*4882a593Smuzhiyun addr -= this->diesize[0];
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun boundary = this->boundary[die];
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun blk = addr >> (this->erase_shift - 1);
241*4882a593Smuzhiyun if (blk > boundary)
242*4882a593Smuzhiyun blk = (blk + boundary + 1) >> 1;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun blk += die ? this->density_mask : 0;
245*4882a593Smuzhiyun return blk;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
onenand_block(struct onenand_chip * this,loff_t addr)248*4882a593Smuzhiyun unsigned int onenand_block(struct onenand_chip *this, loff_t addr)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun if (!FLEXONENAND(this))
251*4882a593Smuzhiyun return addr >> this->erase_shift;
252*4882a593Smuzhiyun return flexonenand_block(this, addr);
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /**
256*4882a593Smuzhiyun * flexonenand_addr - Return address of the block
257*4882a593Smuzhiyun * @this: OneNAND device structure
258*4882a593Smuzhiyun * @block: Block number on Flex-OneNAND
259*4882a593Smuzhiyun *
260*4882a593Smuzhiyun * Return address of the block
261*4882a593Smuzhiyun */
flexonenand_addr(struct onenand_chip * this,int block)262*4882a593Smuzhiyun static loff_t flexonenand_addr(struct onenand_chip *this, int block)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun loff_t ofs = 0;
265*4882a593Smuzhiyun int die = 0, boundary;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
268*4882a593Smuzhiyun block -= this->density_mask;
269*4882a593Smuzhiyun die = 1;
270*4882a593Smuzhiyun ofs = this->diesize[0];
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun boundary = this->boundary[die];
274*4882a593Smuzhiyun ofs += (loff_t) block << (this->erase_shift - 1);
275*4882a593Smuzhiyun if (block > (boundary + 1))
276*4882a593Smuzhiyun ofs += (loff_t) (block - boundary - 1)
277*4882a593Smuzhiyun << (this->erase_shift - 1);
278*4882a593Smuzhiyun return ofs;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
onenand_addr(struct onenand_chip * this,int block)281*4882a593Smuzhiyun loff_t onenand_addr(struct onenand_chip *this, int block)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun if (!FLEXONENAND(this))
284*4882a593Smuzhiyun return (loff_t) block << this->erase_shift;
285*4882a593Smuzhiyun return flexonenand_addr(this, block);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /**
289*4882a593Smuzhiyun * flexonenand_region - [Flex-OneNAND] Return erase region of addr
290*4882a593Smuzhiyun * @param mtd MTD device structure
291*4882a593Smuzhiyun * @param addr address whose erase region needs to be identified
292*4882a593Smuzhiyun */
flexonenand_region(struct mtd_info * mtd,loff_t addr)293*4882a593Smuzhiyun int flexonenand_region(struct mtd_info *mtd, loff_t addr)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun int i;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun for (i = 0; i < mtd->numeraseregions; i++)
298*4882a593Smuzhiyun if (addr < mtd->eraseregions[i].offset)
299*4882a593Smuzhiyun break;
300*4882a593Smuzhiyun return i - 1;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /**
304*4882a593Smuzhiyun * onenand_get_density - [DEFAULT] Get OneNAND density
305*4882a593Smuzhiyun * @param dev_id OneNAND device ID
306*4882a593Smuzhiyun *
307*4882a593Smuzhiyun * Get OneNAND density from device ID
308*4882a593Smuzhiyun */
onenand_get_density(int dev_id)309*4882a593Smuzhiyun static inline int onenand_get_density(int dev_id)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
312*4882a593Smuzhiyun return (density & ONENAND_DEVICE_DENSITY_MASK);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /**
316*4882a593Smuzhiyun * onenand_command - [DEFAULT] Send command to OneNAND device
317*4882a593Smuzhiyun * @param mtd MTD device structure
318*4882a593Smuzhiyun * @param cmd the command to be sent
319*4882a593Smuzhiyun * @param addr offset to read from or write to
320*4882a593Smuzhiyun * @param len number of bytes to read or write
321*4882a593Smuzhiyun *
322*4882a593Smuzhiyun * Send command to OneNAND device. This function is used for middle/large page
323*4882a593Smuzhiyun * devices (1KB/2KB Bytes per page)
324*4882a593Smuzhiyun */
onenand_command(struct mtd_info * mtd,int cmd,loff_t addr,size_t len)325*4882a593Smuzhiyun static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
326*4882a593Smuzhiyun size_t len)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
329*4882a593Smuzhiyun int value;
330*4882a593Smuzhiyun int block, page;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun /* Now we use page size operation */
333*4882a593Smuzhiyun int sectors = 0, count = 0;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /* Address translation */
336*4882a593Smuzhiyun switch (cmd) {
337*4882a593Smuzhiyun case ONENAND_CMD_UNLOCK:
338*4882a593Smuzhiyun case ONENAND_CMD_LOCK:
339*4882a593Smuzhiyun case ONENAND_CMD_LOCK_TIGHT:
340*4882a593Smuzhiyun case ONENAND_CMD_UNLOCK_ALL:
341*4882a593Smuzhiyun block = -1;
342*4882a593Smuzhiyun page = -1;
343*4882a593Smuzhiyun break;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun case FLEXONENAND_CMD_PI_ACCESS:
346*4882a593Smuzhiyun /* addr contains die index */
347*4882a593Smuzhiyun block = addr * this->density_mask;
348*4882a593Smuzhiyun page = -1;
349*4882a593Smuzhiyun break;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun case ONENAND_CMD_ERASE:
352*4882a593Smuzhiyun case ONENAND_CMD_BUFFERRAM:
353*4882a593Smuzhiyun block = onenand_block(this, addr);
354*4882a593Smuzhiyun page = -1;
355*4882a593Smuzhiyun break;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun case FLEXONENAND_CMD_READ_PI:
358*4882a593Smuzhiyun cmd = ONENAND_CMD_READ;
359*4882a593Smuzhiyun block = addr * this->density_mask;
360*4882a593Smuzhiyun page = 0;
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun default:
364*4882a593Smuzhiyun block = onenand_block(this, addr);
365*4882a593Smuzhiyun page = (int) (addr
366*4882a593Smuzhiyun - onenand_addr(this, block)) >> this->page_shift;
367*4882a593Smuzhiyun page &= this->page_mask;
368*4882a593Smuzhiyun break;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /* NOTE: The setting order of the registers is very important! */
372*4882a593Smuzhiyun if (cmd == ONENAND_CMD_BUFFERRAM) {
373*4882a593Smuzhiyun /* Select DataRAM for DDP */
374*4882a593Smuzhiyun value = onenand_bufferram_address(this, block);
375*4882a593Smuzhiyun this->write_word(value,
376*4882a593Smuzhiyun this->base + ONENAND_REG_START_ADDRESS2);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this))
379*4882a593Smuzhiyun ONENAND_SET_BUFFERRAM0(this);
380*4882a593Smuzhiyun else
381*4882a593Smuzhiyun /* Switch to the next data buffer */
382*4882a593Smuzhiyun ONENAND_SET_NEXT_BUFFERRAM(this);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun return 0;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun if (block != -1) {
388*4882a593Smuzhiyun /* Write 'DFS, FBA' of Flash */
389*4882a593Smuzhiyun value = onenand_block_address(this, block);
390*4882a593Smuzhiyun this->write_word(value,
391*4882a593Smuzhiyun this->base + ONENAND_REG_START_ADDRESS1);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun /* Select DataRAM for DDP */
394*4882a593Smuzhiyun value = onenand_bufferram_address(this, block);
395*4882a593Smuzhiyun this->write_word(value,
396*4882a593Smuzhiyun this->base + ONENAND_REG_START_ADDRESS2);
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun if (page != -1) {
400*4882a593Smuzhiyun int dataram;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun switch (cmd) {
403*4882a593Smuzhiyun case FLEXONENAND_CMD_RECOVER_LSB:
404*4882a593Smuzhiyun case ONENAND_CMD_READ:
405*4882a593Smuzhiyun case ONENAND_CMD_READOOB:
406*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this))
407*4882a593Smuzhiyun dataram = ONENAND_SET_BUFFERRAM0(this);
408*4882a593Smuzhiyun else
409*4882a593Smuzhiyun dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun break;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun default:
414*4882a593Smuzhiyun dataram = ONENAND_CURRENT_BUFFERRAM(this);
415*4882a593Smuzhiyun break;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /* Write 'FPA, FSA' of Flash */
419*4882a593Smuzhiyun value = onenand_page_address(page, sectors);
420*4882a593Smuzhiyun this->write_word(value,
421*4882a593Smuzhiyun this->base + ONENAND_REG_START_ADDRESS8);
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* Write 'BSA, BSC' of DataRAM */
424*4882a593Smuzhiyun value = onenand_buffer_address(dataram, sectors, count);
425*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /* Interrupt clear */
429*4882a593Smuzhiyun this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
430*4882a593Smuzhiyun /* Write command */
431*4882a593Smuzhiyun this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /**
437*4882a593Smuzhiyun * onenand_read_ecc - return ecc status
438*4882a593Smuzhiyun * @param this onenand chip structure
439*4882a593Smuzhiyun */
onenand_read_ecc(struct onenand_chip * this)440*4882a593Smuzhiyun static int onenand_read_ecc(struct onenand_chip *this)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun int ecc, i;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (!FLEXONENAND(this))
445*4882a593Smuzhiyun return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
448*4882a593Smuzhiyun ecc = this->read_word(this->base
449*4882a593Smuzhiyun + ((ONENAND_REG_ECC_STATUS + i) << 1));
450*4882a593Smuzhiyun if (likely(!ecc))
451*4882a593Smuzhiyun continue;
452*4882a593Smuzhiyun if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
453*4882a593Smuzhiyun return ONENAND_ECC_2BIT_ALL;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun return 0;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /**
460*4882a593Smuzhiyun * onenand_wait - [DEFAULT] wait until the command is done
461*4882a593Smuzhiyun * @param mtd MTD device structure
462*4882a593Smuzhiyun * @param state state to select the max. timeout value
463*4882a593Smuzhiyun *
464*4882a593Smuzhiyun * Wait for command done. This applies to all OneNAND command
465*4882a593Smuzhiyun * Read can take up to 30us, erase up to 2ms and program up to 350us
466*4882a593Smuzhiyun * according to general OneNAND specs
467*4882a593Smuzhiyun */
onenand_wait(struct mtd_info * mtd,int state)468*4882a593Smuzhiyun static int onenand_wait(struct mtd_info *mtd, int state)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
471*4882a593Smuzhiyun unsigned int interrupt = 0;
472*4882a593Smuzhiyun unsigned int ctrl;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* Wait at most 20ms ... */
475*4882a593Smuzhiyun u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
476*4882a593Smuzhiyun u32 time_start = get_timer(0);
477*4882a593Smuzhiyun do {
478*4882a593Smuzhiyun WATCHDOG_RESET();
479*4882a593Smuzhiyun if (get_timer(time_start) > timeo)
480*4882a593Smuzhiyun return -EIO;
481*4882a593Smuzhiyun interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
482*4882a593Smuzhiyun } while ((interrupt & ONENAND_INT_MASTER) == 0);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun if (interrupt & ONENAND_INT_READ) {
487*4882a593Smuzhiyun int ecc = onenand_read_ecc(this);
488*4882a593Smuzhiyun if (ecc & ONENAND_ECC_2BIT_ALL) {
489*4882a593Smuzhiyun printk("onenand_wait: ECC error = 0x%04x\n", ecc);
490*4882a593Smuzhiyun return -EBADMSG;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (ctrl & ONENAND_CTRL_ERROR) {
495*4882a593Smuzhiyun printk("onenand_wait: controller error = 0x%04x\n", ctrl);
496*4882a593Smuzhiyun if (ctrl & ONENAND_CTRL_LOCK)
497*4882a593Smuzhiyun printk("onenand_wait: it's locked error = 0x%04x\n",
498*4882a593Smuzhiyun ctrl);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return -EIO;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun return 0;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun /**
508*4882a593Smuzhiyun * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
509*4882a593Smuzhiyun * @param mtd MTD data structure
510*4882a593Smuzhiyun * @param area BufferRAM area
511*4882a593Smuzhiyun * @return offset given area
512*4882a593Smuzhiyun *
513*4882a593Smuzhiyun * Return BufferRAM offset given area
514*4882a593Smuzhiyun */
onenand_bufferram_offset(struct mtd_info * mtd,int area)515*4882a593Smuzhiyun static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun if (ONENAND_CURRENT_BUFFERRAM(this)) {
520*4882a593Smuzhiyun if (area == ONENAND_DATARAM)
521*4882a593Smuzhiyun return mtd->writesize;
522*4882a593Smuzhiyun if (area == ONENAND_SPARERAM)
523*4882a593Smuzhiyun return mtd->oobsize;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun return 0;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /**
530*4882a593Smuzhiyun * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
531*4882a593Smuzhiyun * @param mtd MTD data structure
532*4882a593Smuzhiyun * @param area BufferRAM area
533*4882a593Smuzhiyun * @param buffer the databuffer to put/get data
534*4882a593Smuzhiyun * @param offset offset to read from or write to
535*4882a593Smuzhiyun * @param count number of bytes to read/write
536*4882a593Smuzhiyun *
537*4882a593Smuzhiyun * Read the BufferRAM area
538*4882a593Smuzhiyun */
onenand_read_bufferram(struct mtd_info * mtd,loff_t addr,int area,unsigned char * buffer,int offset,size_t count)539*4882a593Smuzhiyun static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
540*4882a593Smuzhiyun unsigned char *buffer, int offset,
541*4882a593Smuzhiyun size_t count)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
544*4882a593Smuzhiyun void __iomem *bufferram;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun bufferram = this->base + area;
547*4882a593Smuzhiyun bufferram += onenand_bufferram_offset(mtd, area);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun memcpy_16(buffer, bufferram + offset, count);
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun return 0;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /**
555*4882a593Smuzhiyun * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
556*4882a593Smuzhiyun * @param mtd MTD data structure
557*4882a593Smuzhiyun * @param area BufferRAM area
558*4882a593Smuzhiyun * @param buffer the databuffer to put/get data
559*4882a593Smuzhiyun * @param offset offset to read from or write to
560*4882a593Smuzhiyun * @param count number of bytes to read/write
561*4882a593Smuzhiyun *
562*4882a593Smuzhiyun * Read the BufferRAM area with Sync. Burst Mode
563*4882a593Smuzhiyun */
onenand_sync_read_bufferram(struct mtd_info * mtd,loff_t addr,int area,unsigned char * buffer,int offset,size_t count)564*4882a593Smuzhiyun static int onenand_sync_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
565*4882a593Smuzhiyun unsigned char *buffer, int offset,
566*4882a593Smuzhiyun size_t count)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
569*4882a593Smuzhiyun void __iomem *bufferram;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun bufferram = this->base + area;
572*4882a593Smuzhiyun bufferram += onenand_bufferram_offset(mtd, area);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun memcpy_16(buffer, bufferram + offset, count);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun this->mmcontrol(mtd, 0);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun return 0;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun /**
584*4882a593Smuzhiyun * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
585*4882a593Smuzhiyun * @param mtd MTD data structure
586*4882a593Smuzhiyun * @param area BufferRAM area
587*4882a593Smuzhiyun * @param buffer the databuffer to put/get data
588*4882a593Smuzhiyun * @param offset offset to read from or write to
589*4882a593Smuzhiyun * @param count number of bytes to read/write
590*4882a593Smuzhiyun *
591*4882a593Smuzhiyun * Write the BufferRAM area
592*4882a593Smuzhiyun */
onenand_write_bufferram(struct mtd_info * mtd,loff_t addr,int area,const unsigned char * buffer,int offset,size_t count)593*4882a593Smuzhiyun static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
594*4882a593Smuzhiyun const unsigned char *buffer, int offset,
595*4882a593Smuzhiyun size_t count)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
598*4882a593Smuzhiyun void __iomem *bufferram;
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun bufferram = this->base + area;
601*4882a593Smuzhiyun bufferram += onenand_bufferram_offset(mtd, area);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun memcpy_16(bufferram + offset, buffer, count);
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun return 0;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun /**
609*4882a593Smuzhiyun * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
610*4882a593Smuzhiyun * @param mtd MTD data structure
611*4882a593Smuzhiyun * @param addr address to check
612*4882a593Smuzhiyun * @return blockpage address
613*4882a593Smuzhiyun *
614*4882a593Smuzhiyun * Get blockpage address at 2x program mode
615*4882a593Smuzhiyun */
onenand_get_2x_blockpage(struct mtd_info * mtd,loff_t addr)616*4882a593Smuzhiyun static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
619*4882a593Smuzhiyun int blockpage, block, page;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /* Calculate the even block number */
622*4882a593Smuzhiyun block = (int) (addr >> this->erase_shift) & ~1;
623*4882a593Smuzhiyun /* Is it the odd plane? */
624*4882a593Smuzhiyun if (addr & this->writesize)
625*4882a593Smuzhiyun block++;
626*4882a593Smuzhiyun page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
627*4882a593Smuzhiyun blockpage = (block << 7) | page;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun return blockpage;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun /**
633*4882a593Smuzhiyun * onenand_check_bufferram - [GENERIC] Check BufferRAM information
634*4882a593Smuzhiyun * @param mtd MTD data structure
635*4882a593Smuzhiyun * @param addr address to check
636*4882a593Smuzhiyun * @return 1 if there are valid data, otherwise 0
637*4882a593Smuzhiyun *
638*4882a593Smuzhiyun * Check bufferram if there is data we required
639*4882a593Smuzhiyun */
onenand_check_bufferram(struct mtd_info * mtd,loff_t addr)640*4882a593Smuzhiyun static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
643*4882a593Smuzhiyun int blockpage, found = 0;
644*4882a593Smuzhiyun unsigned int i;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun if (ONENAND_IS_2PLANE(this))
647*4882a593Smuzhiyun blockpage = onenand_get_2x_blockpage(mtd, addr);
648*4882a593Smuzhiyun else
649*4882a593Smuzhiyun blockpage = (int) (addr >> this->page_shift);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun /* Is there valid data? */
652*4882a593Smuzhiyun i = ONENAND_CURRENT_BUFFERRAM(this);
653*4882a593Smuzhiyun if (this->bufferram[i].blockpage == blockpage)
654*4882a593Smuzhiyun found = 1;
655*4882a593Smuzhiyun else {
656*4882a593Smuzhiyun /* Check another BufferRAM */
657*4882a593Smuzhiyun i = ONENAND_NEXT_BUFFERRAM(this);
658*4882a593Smuzhiyun if (this->bufferram[i].blockpage == blockpage) {
659*4882a593Smuzhiyun ONENAND_SET_NEXT_BUFFERRAM(this);
660*4882a593Smuzhiyun found = 1;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun if (found && ONENAND_IS_DDP(this)) {
665*4882a593Smuzhiyun /* Select DataRAM for DDP */
666*4882a593Smuzhiyun int block = onenand_block(this, addr);
667*4882a593Smuzhiyun int value = onenand_bufferram_address(this, block);
668*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun return found;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun /**
675*4882a593Smuzhiyun * onenand_update_bufferram - [GENERIC] Update BufferRAM information
676*4882a593Smuzhiyun * @param mtd MTD data structure
677*4882a593Smuzhiyun * @param addr address to update
678*4882a593Smuzhiyun * @param valid valid flag
679*4882a593Smuzhiyun *
680*4882a593Smuzhiyun * Update BufferRAM information
681*4882a593Smuzhiyun */
onenand_update_bufferram(struct mtd_info * mtd,loff_t addr,int valid)682*4882a593Smuzhiyun static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
683*4882a593Smuzhiyun int valid)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
686*4882a593Smuzhiyun int blockpage;
687*4882a593Smuzhiyun unsigned int i;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun if (ONENAND_IS_2PLANE(this))
690*4882a593Smuzhiyun blockpage = onenand_get_2x_blockpage(mtd, addr);
691*4882a593Smuzhiyun else
692*4882a593Smuzhiyun blockpage = (int)(addr >> this->page_shift);
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun /* Invalidate another BufferRAM */
695*4882a593Smuzhiyun i = ONENAND_NEXT_BUFFERRAM(this);
696*4882a593Smuzhiyun if (this->bufferram[i].blockpage == blockpage)
697*4882a593Smuzhiyun this->bufferram[i].blockpage = -1;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /* Update BufferRAM */
700*4882a593Smuzhiyun i = ONENAND_CURRENT_BUFFERRAM(this);
701*4882a593Smuzhiyun if (valid)
702*4882a593Smuzhiyun this->bufferram[i].blockpage = blockpage;
703*4882a593Smuzhiyun else
704*4882a593Smuzhiyun this->bufferram[i].blockpage = -1;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun return 0;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun /**
710*4882a593Smuzhiyun * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information
711*4882a593Smuzhiyun * @param mtd MTD data structure
712*4882a593Smuzhiyun * @param addr start address to invalidate
713*4882a593Smuzhiyun * @param len length to invalidate
714*4882a593Smuzhiyun *
715*4882a593Smuzhiyun * Invalidate BufferRAM information
716*4882a593Smuzhiyun */
onenand_invalidate_bufferram(struct mtd_info * mtd,loff_t addr,unsigned int len)717*4882a593Smuzhiyun static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr,
718*4882a593Smuzhiyun unsigned int len)
719*4882a593Smuzhiyun {
720*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
721*4882a593Smuzhiyun int i;
722*4882a593Smuzhiyun loff_t end_addr = addr + len;
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun /* Invalidate BufferRAM */
725*4882a593Smuzhiyun for (i = 0; i < MAX_BUFFERRAM; i++) {
726*4882a593Smuzhiyun loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun if (buf_addr >= addr && buf_addr < end_addr)
729*4882a593Smuzhiyun this->bufferram[i].blockpage = -1;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun /**
734*4882a593Smuzhiyun * onenand_get_device - [GENERIC] Get chip for selected access
735*4882a593Smuzhiyun * @param mtd MTD device structure
736*4882a593Smuzhiyun * @param new_state the state which is requested
737*4882a593Smuzhiyun *
738*4882a593Smuzhiyun * Get the device and lock it for exclusive access
739*4882a593Smuzhiyun */
onenand_get_device(struct mtd_info * mtd,int new_state)740*4882a593Smuzhiyun static void onenand_get_device(struct mtd_info *mtd, int new_state)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun /* Do nothing */
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun /**
746*4882a593Smuzhiyun * onenand_release_device - [GENERIC] release chip
747*4882a593Smuzhiyun * @param mtd MTD device structure
748*4882a593Smuzhiyun *
749*4882a593Smuzhiyun * Deselect, release chip lock and wake up anyone waiting on the device
750*4882a593Smuzhiyun */
onenand_release_device(struct mtd_info * mtd)751*4882a593Smuzhiyun static void onenand_release_device(struct mtd_info *mtd)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun /* Do nothing */
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /**
757*4882a593Smuzhiyun * onenand_transfer_auto_oob - [INTERN] oob auto-placement transfer
758*4882a593Smuzhiyun * @param mtd MTD device structure
759*4882a593Smuzhiyun * @param buf destination address
760*4882a593Smuzhiyun * @param column oob offset to read from
761*4882a593Smuzhiyun * @param thislen oob length to read
762*4882a593Smuzhiyun */
onenand_transfer_auto_oob(struct mtd_info * mtd,uint8_t * buf,int column,int thislen)763*4882a593Smuzhiyun static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf,
764*4882a593Smuzhiyun int column, int thislen)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
767*4882a593Smuzhiyun struct nand_oobfree *free;
768*4882a593Smuzhiyun int readcol = column;
769*4882a593Smuzhiyun int readend = column + thislen;
770*4882a593Smuzhiyun int lastgap = 0;
771*4882a593Smuzhiyun unsigned int i;
772*4882a593Smuzhiyun uint8_t *oob_buf = this->oob_buf;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun free = this->ecclayout->oobfree;
775*4882a593Smuzhiyun for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
776*4882a593Smuzhiyun i++, free++) {
777*4882a593Smuzhiyun if (readcol >= lastgap)
778*4882a593Smuzhiyun readcol += free->offset - lastgap;
779*4882a593Smuzhiyun if (readend >= lastgap)
780*4882a593Smuzhiyun readend += free->offset - lastgap;
781*4882a593Smuzhiyun lastgap = free->offset + free->length;
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
784*4882a593Smuzhiyun free = this->ecclayout->oobfree;
785*4882a593Smuzhiyun for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
786*4882a593Smuzhiyun i++, free++) {
787*4882a593Smuzhiyun int free_end = free->offset + free->length;
788*4882a593Smuzhiyun if (free->offset < readend && free_end > readcol) {
789*4882a593Smuzhiyun int st = max_t(int,free->offset,readcol);
790*4882a593Smuzhiyun int ed = min_t(int,free_end,readend);
791*4882a593Smuzhiyun int n = ed - st;
792*4882a593Smuzhiyun memcpy(buf, oob_buf + st, n);
793*4882a593Smuzhiyun buf += n;
794*4882a593Smuzhiyun } else if (column == 0)
795*4882a593Smuzhiyun break;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun return 0;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun /**
801*4882a593Smuzhiyun * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
802*4882a593Smuzhiyun * @param mtd MTD device structure
803*4882a593Smuzhiyun * @param addr address to recover
804*4882a593Smuzhiyun * @param status return value from onenand_wait
805*4882a593Smuzhiyun *
806*4882a593Smuzhiyun * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
807*4882a593Smuzhiyun * lower page address and MSB page has higher page address in paired pages.
808*4882a593Smuzhiyun * If power off occurs during MSB page program, the paired LSB page data can
809*4882a593Smuzhiyun * become corrupt. LSB page recovery read is a way to read LSB page though page
810*4882a593Smuzhiyun * data are corrupted. When uncorrectable error occurs as a result of LSB page
811*4882a593Smuzhiyun * read after power up, issue LSB page recovery read.
812*4882a593Smuzhiyun */
onenand_recover_lsb(struct mtd_info * mtd,loff_t addr,int status)813*4882a593Smuzhiyun static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
816*4882a593Smuzhiyun int i;
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun /* Recovery is only for Flex-OneNAND */
819*4882a593Smuzhiyun if (!FLEXONENAND(this))
820*4882a593Smuzhiyun return status;
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun /* check if we failed due to uncorrectable error */
823*4882a593Smuzhiyun if (!mtd_is_eccerr(status) && status != ONENAND_BBT_READ_ECC_ERROR)
824*4882a593Smuzhiyun return status;
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun /* check if address lies in MLC region */
827*4882a593Smuzhiyun i = flexonenand_region(mtd, addr);
828*4882a593Smuzhiyun if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
829*4882a593Smuzhiyun return status;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun printk("onenand_recover_lsb:"
832*4882a593Smuzhiyun "Attempting to recover from uncorrectable read\n");
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /* Issue the LSB page recovery command */
835*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
836*4882a593Smuzhiyun return this->wait(mtd, FL_READING);
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun /**
840*4882a593Smuzhiyun * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
841*4882a593Smuzhiyun * @param mtd MTD device structure
842*4882a593Smuzhiyun * @param from offset to read from
843*4882a593Smuzhiyun * @param ops oob operation description structure
844*4882a593Smuzhiyun *
845*4882a593Smuzhiyun * OneNAND read main and/or out-of-band data
846*4882a593Smuzhiyun */
onenand_read_ops_nolock(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)847*4882a593Smuzhiyun static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from,
848*4882a593Smuzhiyun struct mtd_oob_ops *ops)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
851*4882a593Smuzhiyun struct mtd_ecc_stats stats;
852*4882a593Smuzhiyun size_t len = ops->len;
853*4882a593Smuzhiyun size_t ooblen = ops->ooblen;
854*4882a593Smuzhiyun u_char *buf = ops->datbuf;
855*4882a593Smuzhiyun u_char *oobbuf = ops->oobbuf;
856*4882a593Smuzhiyun int read = 0, column, thislen;
857*4882a593Smuzhiyun int oobread = 0, oobcolumn, thisooblen, oobsize;
858*4882a593Smuzhiyun int ret = 0, boundary = 0;
859*4882a593Smuzhiyun int writesize = this->writesize;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun pr_debug("onenand_read_ops_nolock: from = 0x%08x, len = %i\n",
862*4882a593Smuzhiyun (unsigned int) from, (int) len);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun if (ops->mode == MTD_OPS_AUTO_OOB)
865*4882a593Smuzhiyun oobsize = this->ecclayout->oobavail;
866*4882a593Smuzhiyun else
867*4882a593Smuzhiyun oobsize = mtd->oobsize;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun oobcolumn = from & (mtd->oobsize - 1);
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun /* Do not allow reads past end of device */
872*4882a593Smuzhiyun if ((from + len) > mtd->size) {
873*4882a593Smuzhiyun printk(KERN_ERR "onenand_read_ops_nolock: Attempt read beyond end of device\n");
874*4882a593Smuzhiyun ops->retlen = 0;
875*4882a593Smuzhiyun ops->oobretlen = 0;
876*4882a593Smuzhiyun return -EINVAL;
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun stats = mtd->ecc_stats;
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun /* Read-while-load method */
882*4882a593Smuzhiyun /* Note: We can't use this feature in MLC */
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun /* Do first load to bufferRAM */
885*4882a593Smuzhiyun if (read < len) {
886*4882a593Smuzhiyun if (!onenand_check_bufferram(mtd, from)) {
887*4882a593Smuzhiyun this->main_buf = buf;
888*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_READ, from, writesize);
889*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
890*4882a593Smuzhiyun if (unlikely(ret))
891*4882a593Smuzhiyun ret = onenand_recover_lsb(mtd, from, ret);
892*4882a593Smuzhiyun onenand_update_bufferram(mtd, from, !ret);
893*4882a593Smuzhiyun if (ret == -EBADMSG)
894*4882a593Smuzhiyun ret = 0;
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun thislen = min_t(int, writesize, len - read);
899*4882a593Smuzhiyun column = from & (writesize - 1);
900*4882a593Smuzhiyun if (column + thislen > writesize)
901*4882a593Smuzhiyun thislen = writesize - column;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun while (!ret) {
904*4882a593Smuzhiyun /* If there is more to load then start next load */
905*4882a593Smuzhiyun from += thislen;
906*4882a593Smuzhiyun if (!ONENAND_IS_4KB_PAGE(this) && read + thislen < len) {
907*4882a593Smuzhiyun this->main_buf = buf + thislen;
908*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_READ, from, writesize);
909*4882a593Smuzhiyun /*
910*4882a593Smuzhiyun * Chip boundary handling in DDP
911*4882a593Smuzhiyun * Now we issued chip 1 read and pointed chip 1
912*4882a593Smuzhiyun * bufferam so we have to point chip 0 bufferam.
913*4882a593Smuzhiyun */
914*4882a593Smuzhiyun if (ONENAND_IS_DDP(this) &&
915*4882a593Smuzhiyun unlikely(from == (this->chipsize >> 1))) {
916*4882a593Smuzhiyun this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2);
917*4882a593Smuzhiyun boundary = 1;
918*4882a593Smuzhiyun } else
919*4882a593Smuzhiyun boundary = 0;
920*4882a593Smuzhiyun ONENAND_SET_PREV_BUFFERRAM(this);
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun /* While load is going, read from last bufferRAM */
924*4882a593Smuzhiyun this->read_bufferram(mtd, from - thislen, ONENAND_DATARAM, buf, column, thislen);
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun /* Read oob area if needed */
927*4882a593Smuzhiyun if (oobbuf) {
928*4882a593Smuzhiyun thisooblen = oobsize - oobcolumn;
929*4882a593Smuzhiyun thisooblen = min_t(int, thisooblen, ooblen - oobread);
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun if (ops->mode == MTD_OPS_AUTO_OOB)
932*4882a593Smuzhiyun onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
933*4882a593Smuzhiyun else
934*4882a593Smuzhiyun this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
935*4882a593Smuzhiyun oobread += thisooblen;
936*4882a593Smuzhiyun oobbuf += thisooblen;
937*4882a593Smuzhiyun oobcolumn = 0;
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this) && (read + thislen < len)) {
941*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_READ, from, writesize);
942*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
943*4882a593Smuzhiyun if (unlikely(ret))
944*4882a593Smuzhiyun ret = onenand_recover_lsb(mtd, from, ret);
945*4882a593Smuzhiyun onenand_update_bufferram(mtd, from, !ret);
946*4882a593Smuzhiyun if (mtd_is_eccerr(ret))
947*4882a593Smuzhiyun ret = 0;
948*4882a593Smuzhiyun }
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun /* See if we are done */
951*4882a593Smuzhiyun read += thislen;
952*4882a593Smuzhiyun if (read == len)
953*4882a593Smuzhiyun break;
954*4882a593Smuzhiyun /* Set up for next read from bufferRAM */
955*4882a593Smuzhiyun if (unlikely(boundary))
956*4882a593Smuzhiyun this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
957*4882a593Smuzhiyun if (!ONENAND_IS_4KB_PAGE(this))
958*4882a593Smuzhiyun ONENAND_SET_NEXT_BUFFERRAM(this);
959*4882a593Smuzhiyun buf += thislen;
960*4882a593Smuzhiyun thislen = min_t(int, writesize, len - read);
961*4882a593Smuzhiyun column = 0;
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun if (!ONENAND_IS_4KB_PAGE(this)) {
964*4882a593Smuzhiyun /* Now wait for load */
965*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
966*4882a593Smuzhiyun onenand_update_bufferram(mtd, from, !ret);
967*4882a593Smuzhiyun if (mtd_is_eccerr(ret))
968*4882a593Smuzhiyun ret = 0;
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun /*
973*4882a593Smuzhiyun * Return success, if no ECC failures, else -EBADMSG
974*4882a593Smuzhiyun * fs driver will take care of that, because
975*4882a593Smuzhiyun * retlen == desired len and result == -EBADMSG
976*4882a593Smuzhiyun */
977*4882a593Smuzhiyun ops->retlen = read;
978*4882a593Smuzhiyun ops->oobretlen = oobread;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun if (ret)
981*4882a593Smuzhiyun return ret;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (mtd->ecc_stats.failed - stats.failed)
984*4882a593Smuzhiyun return -EBADMSG;
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun /* return max bitflips per ecc step; ONENANDs correct 1 bit only */
987*4882a593Smuzhiyun return mtd->ecc_stats.corrected != stats.corrected ? 1 : 0;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun /**
991*4882a593Smuzhiyun * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
992*4882a593Smuzhiyun * @param mtd MTD device structure
993*4882a593Smuzhiyun * @param from offset to read from
994*4882a593Smuzhiyun * @param ops oob operation description structure
995*4882a593Smuzhiyun *
996*4882a593Smuzhiyun * OneNAND read out-of-band data from the spare area
997*4882a593Smuzhiyun */
onenand_read_oob_nolock(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)998*4882a593Smuzhiyun static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from,
999*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1000*4882a593Smuzhiyun {
1001*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1002*4882a593Smuzhiyun struct mtd_ecc_stats stats;
1003*4882a593Smuzhiyun int read = 0, thislen, column, oobsize;
1004*4882a593Smuzhiyun size_t len = ops->ooblen;
1005*4882a593Smuzhiyun unsigned int mode = ops->mode;
1006*4882a593Smuzhiyun u_char *buf = ops->oobbuf;
1007*4882a593Smuzhiyun int ret = 0, readcmd;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun from += ops->ooboffs;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun pr_debug("onenand_read_oob_nolock: from = 0x%08x, len = %i\n",
1012*4882a593Smuzhiyun (unsigned int) from, (int) len);
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun /* Initialize return length value */
1015*4882a593Smuzhiyun ops->oobretlen = 0;
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun if (mode == MTD_OPS_AUTO_OOB)
1018*4882a593Smuzhiyun oobsize = this->ecclayout->oobavail;
1019*4882a593Smuzhiyun else
1020*4882a593Smuzhiyun oobsize = mtd->oobsize;
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun column = from & (mtd->oobsize - 1);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun if (unlikely(column >= oobsize)) {
1025*4882a593Smuzhiyun printk(KERN_ERR "onenand_read_oob_nolock: Attempted to start read outside oob\n");
1026*4882a593Smuzhiyun return -EINVAL;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun /* Do not allow reads past end of device */
1030*4882a593Smuzhiyun if (unlikely(from >= mtd->size ||
1031*4882a593Smuzhiyun column + len > ((mtd->size >> this->page_shift) -
1032*4882a593Smuzhiyun (from >> this->page_shift)) * oobsize)) {
1033*4882a593Smuzhiyun printk(KERN_ERR "onenand_read_oob_nolock: Attempted to read beyond end of device\n");
1034*4882a593Smuzhiyun return -EINVAL;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun stats = mtd->ecc_stats;
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun readcmd = ONENAND_IS_4KB_PAGE(this) ?
1040*4882a593Smuzhiyun ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun while (read < len) {
1043*4882a593Smuzhiyun thislen = oobsize - column;
1044*4882a593Smuzhiyun thislen = min_t(int, thislen, len);
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun this->spare_buf = buf;
1047*4882a593Smuzhiyun this->command(mtd, readcmd, from, mtd->oobsize);
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun onenand_update_bufferram(mtd, from, 0);
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
1052*4882a593Smuzhiyun if (unlikely(ret))
1053*4882a593Smuzhiyun ret = onenand_recover_lsb(mtd, from, ret);
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun if (ret && ret != -EBADMSG) {
1056*4882a593Smuzhiyun printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret);
1057*4882a593Smuzhiyun break;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun if (mode == MTD_OPS_AUTO_OOB)
1061*4882a593Smuzhiyun onenand_transfer_auto_oob(mtd, buf, column, thislen);
1062*4882a593Smuzhiyun else
1063*4882a593Smuzhiyun this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen);
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun read += thislen;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun if (read == len)
1068*4882a593Smuzhiyun break;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun buf += thislen;
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun /* Read more? */
1073*4882a593Smuzhiyun if (read < len) {
1074*4882a593Smuzhiyun /* Page size */
1075*4882a593Smuzhiyun from += mtd->writesize;
1076*4882a593Smuzhiyun column = 0;
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun ops->oobretlen = read;
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun if (ret)
1083*4882a593Smuzhiyun return ret;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun if (mtd->ecc_stats.failed - stats.failed)
1086*4882a593Smuzhiyun return -EBADMSG;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun return 0;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun /**
1092*4882a593Smuzhiyun * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
1093*4882a593Smuzhiyun * @param mtd MTD device structure
1094*4882a593Smuzhiyun * @param from offset to read from
1095*4882a593Smuzhiyun * @param len number of bytes to read
1096*4882a593Smuzhiyun * @param retlen pointer to variable to store the number of read bytes
1097*4882a593Smuzhiyun * @param buf the databuffer to put data
1098*4882a593Smuzhiyun *
1099*4882a593Smuzhiyun * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
1100*4882a593Smuzhiyun */
onenand_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1101*4882a593Smuzhiyun int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
1102*4882a593Smuzhiyun size_t * retlen, u_char * buf)
1103*4882a593Smuzhiyun {
1104*4882a593Smuzhiyun struct mtd_oob_ops ops = {
1105*4882a593Smuzhiyun .len = len,
1106*4882a593Smuzhiyun .ooblen = 0,
1107*4882a593Smuzhiyun .datbuf = buf,
1108*4882a593Smuzhiyun .oobbuf = NULL,
1109*4882a593Smuzhiyun };
1110*4882a593Smuzhiyun int ret;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun onenand_get_device(mtd, FL_READING);
1113*4882a593Smuzhiyun ret = onenand_read_ops_nolock(mtd, from, &ops);
1114*4882a593Smuzhiyun onenand_release_device(mtd);
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun *retlen = ops.retlen;
1117*4882a593Smuzhiyun return ret;
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun /**
1121*4882a593Smuzhiyun * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
1122*4882a593Smuzhiyun * @param mtd MTD device structure
1123*4882a593Smuzhiyun * @param from offset to read from
1124*4882a593Smuzhiyun * @param ops oob operations description structure
1125*4882a593Smuzhiyun *
1126*4882a593Smuzhiyun * OneNAND main and/or out-of-band
1127*4882a593Smuzhiyun */
onenand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)1128*4882a593Smuzhiyun int onenand_read_oob(struct mtd_info *mtd, loff_t from,
1129*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1130*4882a593Smuzhiyun {
1131*4882a593Smuzhiyun int ret;
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun switch (ops->mode) {
1134*4882a593Smuzhiyun case MTD_OPS_PLACE_OOB:
1135*4882a593Smuzhiyun case MTD_OPS_AUTO_OOB:
1136*4882a593Smuzhiyun break;
1137*4882a593Smuzhiyun case MTD_OPS_RAW:
1138*4882a593Smuzhiyun /* Not implemented yet */
1139*4882a593Smuzhiyun default:
1140*4882a593Smuzhiyun return -EINVAL;
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun onenand_get_device(mtd, FL_READING);
1144*4882a593Smuzhiyun if (ops->datbuf)
1145*4882a593Smuzhiyun ret = onenand_read_ops_nolock(mtd, from, ops);
1146*4882a593Smuzhiyun else
1147*4882a593Smuzhiyun ret = onenand_read_oob_nolock(mtd, from, ops);
1148*4882a593Smuzhiyun onenand_release_device(mtd);
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun return ret;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun /**
1154*4882a593Smuzhiyun * onenand_bbt_wait - [DEFAULT] wait until the command is done
1155*4882a593Smuzhiyun * @param mtd MTD device structure
1156*4882a593Smuzhiyun * @param state state to select the max. timeout value
1157*4882a593Smuzhiyun *
1158*4882a593Smuzhiyun * Wait for command done.
1159*4882a593Smuzhiyun */
onenand_bbt_wait(struct mtd_info * mtd,int state)1160*4882a593Smuzhiyun static int onenand_bbt_wait(struct mtd_info *mtd, int state)
1161*4882a593Smuzhiyun {
1162*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1163*4882a593Smuzhiyun unsigned int interrupt;
1164*4882a593Smuzhiyun unsigned int ctrl;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun /* Wait at most 20ms ... */
1167*4882a593Smuzhiyun u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
1168*4882a593Smuzhiyun u32 time_start = get_timer(0);
1169*4882a593Smuzhiyun do {
1170*4882a593Smuzhiyun WATCHDOG_RESET();
1171*4882a593Smuzhiyun if (get_timer(time_start) > timeo)
1172*4882a593Smuzhiyun return ONENAND_BBT_READ_FATAL_ERROR;
1173*4882a593Smuzhiyun interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1174*4882a593Smuzhiyun } while ((interrupt & ONENAND_INT_MASTER) == 0);
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun /* To get correct interrupt status in timeout case */
1177*4882a593Smuzhiyun interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1178*4882a593Smuzhiyun ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun if (interrupt & ONENAND_INT_READ) {
1181*4882a593Smuzhiyun int ecc = onenand_read_ecc(this);
1182*4882a593Smuzhiyun if (ecc & ONENAND_ECC_2BIT_ALL) {
1183*4882a593Smuzhiyun printk(KERN_INFO "onenand_bbt_wait: ecc error = 0x%04x"
1184*4882a593Smuzhiyun ", controller = 0x%04x\n", ecc, ctrl);
1185*4882a593Smuzhiyun return ONENAND_BBT_READ_ERROR;
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun } else {
1188*4882a593Smuzhiyun printk(KERN_ERR "onenand_bbt_wait: read timeout!"
1189*4882a593Smuzhiyun "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
1190*4882a593Smuzhiyun return ONENAND_BBT_READ_FATAL_ERROR;
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun /* Initial bad block case: 0x2400 or 0x0400 */
1194*4882a593Smuzhiyun if (ctrl & ONENAND_CTRL_ERROR) {
1195*4882a593Smuzhiyun printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl);
1196*4882a593Smuzhiyun return ONENAND_BBT_READ_ERROR;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun return 0;
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun /**
1203*4882a593Smuzhiyun * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
1204*4882a593Smuzhiyun * @param mtd MTD device structure
1205*4882a593Smuzhiyun * @param from offset to read from
1206*4882a593Smuzhiyun * @param ops oob operation description structure
1207*4882a593Smuzhiyun *
1208*4882a593Smuzhiyun * OneNAND read out-of-band data from the spare area for bbt scan
1209*4882a593Smuzhiyun */
onenand_bbt_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)1210*4882a593Smuzhiyun int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
1211*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1214*4882a593Smuzhiyun int read = 0, thislen, column;
1215*4882a593Smuzhiyun int ret = 0, readcmd;
1216*4882a593Smuzhiyun size_t len = ops->ooblen;
1217*4882a593Smuzhiyun u_char *buf = ops->oobbuf;
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun pr_debug("onenand_bbt_read_oob: from = 0x%08x, len = %zi\n",
1220*4882a593Smuzhiyun (unsigned int) from, len);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun readcmd = ONENAND_IS_4KB_PAGE(this) ?
1223*4882a593Smuzhiyun ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun /* Initialize return value */
1226*4882a593Smuzhiyun ops->oobretlen = 0;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /* Do not allow reads past end of device */
1229*4882a593Smuzhiyun if (unlikely((from + len) > mtd->size)) {
1230*4882a593Smuzhiyun printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n");
1231*4882a593Smuzhiyun return ONENAND_BBT_READ_FATAL_ERROR;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun /* Grab the lock and see if the device is available */
1235*4882a593Smuzhiyun onenand_get_device(mtd, FL_READING);
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun column = from & (mtd->oobsize - 1);
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun while (read < len) {
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun thislen = mtd->oobsize - column;
1242*4882a593Smuzhiyun thislen = min_t(int, thislen, len);
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun this->spare_buf = buf;
1245*4882a593Smuzhiyun this->command(mtd, readcmd, from, mtd->oobsize);
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun onenand_update_bufferram(mtd, from, 0);
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun ret = this->bbt_wait(mtd, FL_READING);
1250*4882a593Smuzhiyun if (unlikely(ret))
1251*4882a593Smuzhiyun ret = onenand_recover_lsb(mtd, from, ret);
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun if (ret)
1254*4882a593Smuzhiyun break;
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen);
1257*4882a593Smuzhiyun read += thislen;
1258*4882a593Smuzhiyun if (read == len)
1259*4882a593Smuzhiyun break;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun buf += thislen;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun /* Read more? */
1264*4882a593Smuzhiyun if (read < len) {
1265*4882a593Smuzhiyun /* Update Page size */
1266*4882a593Smuzhiyun from += this->writesize;
1267*4882a593Smuzhiyun column = 0;
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun }
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun /* Deselect and wake up anyone waiting on the device */
1272*4882a593Smuzhiyun onenand_release_device(mtd);
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun ops->oobretlen = read;
1275*4882a593Smuzhiyun return ret;
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
1280*4882a593Smuzhiyun /**
1281*4882a593Smuzhiyun * onenand_verify_oob - [GENERIC] verify the oob contents after a write
1282*4882a593Smuzhiyun * @param mtd MTD device structure
1283*4882a593Smuzhiyun * @param buf the databuffer to verify
1284*4882a593Smuzhiyun * @param to offset to read from
1285*4882a593Smuzhiyun */
onenand_verify_oob(struct mtd_info * mtd,const u_char * buf,loff_t to)1286*4882a593Smuzhiyun static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to)
1287*4882a593Smuzhiyun {
1288*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1289*4882a593Smuzhiyun u_char *oob_buf = this->oob_buf;
1290*4882a593Smuzhiyun int status, i, readcmd;
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun readcmd = ONENAND_IS_4KB_PAGE(this) ?
1293*4882a593Smuzhiyun ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun this->command(mtd, readcmd, to, mtd->oobsize);
1296*4882a593Smuzhiyun onenand_update_bufferram(mtd, to, 0);
1297*4882a593Smuzhiyun status = this->wait(mtd, FL_READING);
1298*4882a593Smuzhiyun if (status)
1299*4882a593Smuzhiyun return status;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
1302*4882a593Smuzhiyun for (i = 0; i < mtd->oobsize; i++)
1303*4882a593Smuzhiyun if (buf[i] != 0xFF && buf[i] != oob_buf[i])
1304*4882a593Smuzhiyun return -EBADMSG;
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun return 0;
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun /**
1310*4882a593Smuzhiyun * onenand_verify - [GENERIC] verify the chip contents after a write
1311*4882a593Smuzhiyun * @param mtd MTD device structure
1312*4882a593Smuzhiyun * @param buf the databuffer to verify
1313*4882a593Smuzhiyun * @param addr offset to read from
1314*4882a593Smuzhiyun * @param len number of bytes to read and compare
1315*4882a593Smuzhiyun */
onenand_verify(struct mtd_info * mtd,const u_char * buf,loff_t addr,size_t len)1316*4882a593Smuzhiyun static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len)
1317*4882a593Smuzhiyun {
1318*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1319*4882a593Smuzhiyun void __iomem *dataram;
1320*4882a593Smuzhiyun int ret = 0;
1321*4882a593Smuzhiyun int thislen, column;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun while (len != 0) {
1324*4882a593Smuzhiyun thislen = min_t(int, this->writesize, len);
1325*4882a593Smuzhiyun column = addr & (this->writesize - 1);
1326*4882a593Smuzhiyun if (column + thislen > this->writesize)
1327*4882a593Smuzhiyun thislen = this->writesize - column;
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun onenand_update_bufferram(mtd, addr, 0);
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
1334*4882a593Smuzhiyun if (ret)
1335*4882a593Smuzhiyun return ret;
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun onenand_update_bufferram(mtd, addr, 1);
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun dataram = this->base + ONENAND_DATARAM;
1340*4882a593Smuzhiyun dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM);
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun if (memcmp(buf, dataram + column, thislen))
1343*4882a593Smuzhiyun return -EBADMSG;
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun len -= thislen;
1346*4882a593Smuzhiyun buf += thislen;
1347*4882a593Smuzhiyun addr += thislen;
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun return 0;
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun #else
1353*4882a593Smuzhiyun #define onenand_verify(...) (0)
1354*4882a593Smuzhiyun #define onenand_verify_oob(...) (0)
1355*4882a593Smuzhiyun #endif
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun #define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0)
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun /**
1360*4882a593Smuzhiyun * onenand_fill_auto_oob - [INTERN] oob auto-placement transfer
1361*4882a593Smuzhiyun * @param mtd MTD device structure
1362*4882a593Smuzhiyun * @param oob_buf oob buffer
1363*4882a593Smuzhiyun * @param buf source address
1364*4882a593Smuzhiyun * @param column oob offset to write to
1365*4882a593Smuzhiyun * @param thislen oob length to write
1366*4882a593Smuzhiyun */
onenand_fill_auto_oob(struct mtd_info * mtd,u_char * oob_buf,const u_char * buf,int column,int thislen)1367*4882a593Smuzhiyun static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
1368*4882a593Smuzhiyun const u_char *buf, int column, int thislen)
1369*4882a593Smuzhiyun {
1370*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1371*4882a593Smuzhiyun struct nand_oobfree *free;
1372*4882a593Smuzhiyun int writecol = column;
1373*4882a593Smuzhiyun int writeend = column + thislen;
1374*4882a593Smuzhiyun int lastgap = 0;
1375*4882a593Smuzhiyun unsigned int i;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun free = this->ecclayout->oobfree;
1378*4882a593Smuzhiyun for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
1379*4882a593Smuzhiyun i++, free++) {
1380*4882a593Smuzhiyun if (writecol >= lastgap)
1381*4882a593Smuzhiyun writecol += free->offset - lastgap;
1382*4882a593Smuzhiyun if (writeend >= lastgap)
1383*4882a593Smuzhiyun writeend += free->offset - lastgap;
1384*4882a593Smuzhiyun lastgap = free->offset + free->length;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun free = this->ecclayout->oobfree;
1387*4882a593Smuzhiyun for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
1388*4882a593Smuzhiyun i++, free++) {
1389*4882a593Smuzhiyun int free_end = free->offset + free->length;
1390*4882a593Smuzhiyun if (free->offset < writeend && free_end > writecol) {
1391*4882a593Smuzhiyun int st = max_t(int,free->offset,writecol);
1392*4882a593Smuzhiyun int ed = min_t(int,free_end,writeend);
1393*4882a593Smuzhiyun int n = ed - st;
1394*4882a593Smuzhiyun memcpy(oob_buf + st, buf, n);
1395*4882a593Smuzhiyun buf += n;
1396*4882a593Smuzhiyun } else if (column == 0)
1397*4882a593Smuzhiyun break;
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun return 0;
1400*4882a593Smuzhiyun }
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun /**
1403*4882a593Smuzhiyun * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
1404*4882a593Smuzhiyun * @param mtd MTD device structure
1405*4882a593Smuzhiyun * @param to offset to write to
1406*4882a593Smuzhiyun * @param ops oob operation description structure
1407*4882a593Smuzhiyun *
1408*4882a593Smuzhiyun * Write main and/or oob with ECC
1409*4882a593Smuzhiyun */
onenand_write_ops_nolock(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)1410*4882a593Smuzhiyun static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to,
1411*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1412*4882a593Smuzhiyun {
1413*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1414*4882a593Smuzhiyun int written = 0, column, thislen, subpage;
1415*4882a593Smuzhiyun int oobwritten = 0, oobcolumn, thisooblen, oobsize;
1416*4882a593Smuzhiyun size_t len = ops->len;
1417*4882a593Smuzhiyun size_t ooblen = ops->ooblen;
1418*4882a593Smuzhiyun const u_char *buf = ops->datbuf;
1419*4882a593Smuzhiyun const u_char *oob = ops->oobbuf;
1420*4882a593Smuzhiyun u_char *oobbuf;
1421*4882a593Smuzhiyun int ret = 0;
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun pr_debug("onenand_write_ops_nolock: to = 0x%08x, len = %i\n",
1424*4882a593Smuzhiyun (unsigned int) to, (int) len);
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun /* Initialize retlen, in case of early exit */
1427*4882a593Smuzhiyun ops->retlen = 0;
1428*4882a593Smuzhiyun ops->oobretlen = 0;
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun /* Reject writes, which are not page aligned */
1431*4882a593Smuzhiyun if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
1432*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_ops_nolock: Attempt to write not page aligned data\n");
1433*4882a593Smuzhiyun return -EINVAL;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun if (ops->mode == MTD_OPS_AUTO_OOB)
1437*4882a593Smuzhiyun oobsize = this->ecclayout->oobavail;
1438*4882a593Smuzhiyun else
1439*4882a593Smuzhiyun oobsize = mtd->oobsize;
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun oobcolumn = to & (mtd->oobsize - 1);
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun column = to & (mtd->writesize - 1);
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun /* Loop until all data write */
1446*4882a593Smuzhiyun while (written < len) {
1447*4882a593Smuzhiyun u_char *wbuf = (u_char *) buf;
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun thislen = min_t(int, mtd->writesize - column, len - written);
1450*4882a593Smuzhiyun thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten);
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun /* Partial page write */
1455*4882a593Smuzhiyun subpage = thislen < mtd->writesize;
1456*4882a593Smuzhiyun if (subpage) {
1457*4882a593Smuzhiyun memset(this->page_buf, 0xff, mtd->writesize);
1458*4882a593Smuzhiyun memcpy(this->page_buf + column, buf, thislen);
1459*4882a593Smuzhiyun wbuf = this->page_buf;
1460*4882a593Smuzhiyun }
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun this->write_bufferram(mtd, to, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun if (oob) {
1465*4882a593Smuzhiyun oobbuf = this->oob_buf;
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun /* We send data to spare ram with oobsize
1468*4882a593Smuzhiyun * * to prevent byte access */
1469*4882a593Smuzhiyun memset(oobbuf, 0xff, mtd->oobsize);
1470*4882a593Smuzhiyun if (ops->mode == MTD_OPS_AUTO_OOB)
1471*4882a593Smuzhiyun onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
1472*4882a593Smuzhiyun else
1473*4882a593Smuzhiyun memcpy(oobbuf + oobcolumn, oob, thisooblen);
1474*4882a593Smuzhiyun
1475*4882a593Smuzhiyun oobwritten += thisooblen;
1476*4882a593Smuzhiyun oob += thisooblen;
1477*4882a593Smuzhiyun oobcolumn = 0;
1478*4882a593Smuzhiyun } else
1479*4882a593Smuzhiyun oobbuf = (u_char *) ffchars;
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
1482*4882a593Smuzhiyun
1483*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun ret = this->wait(mtd, FL_WRITING);
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun /* In partial page write we don't update bufferram */
1488*4882a593Smuzhiyun onenand_update_bufferram(mtd, to, !ret && !subpage);
1489*4882a593Smuzhiyun if (ONENAND_IS_2PLANE(this)) {
1490*4882a593Smuzhiyun ONENAND_SET_BUFFERRAM1(this);
1491*4882a593Smuzhiyun onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun if (ret) {
1495*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret);
1496*4882a593Smuzhiyun break;
1497*4882a593Smuzhiyun }
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun /* Only check verify write turn on */
1500*4882a593Smuzhiyun ret = onenand_verify(mtd, buf, to, thislen);
1501*4882a593Smuzhiyun if (ret) {
1502*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_ops_nolock: verify failed %d\n", ret);
1503*4882a593Smuzhiyun break;
1504*4882a593Smuzhiyun }
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun written += thislen;
1507*4882a593Smuzhiyun
1508*4882a593Smuzhiyun if (written == len)
1509*4882a593Smuzhiyun break;
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun column = 0;
1512*4882a593Smuzhiyun to += thislen;
1513*4882a593Smuzhiyun buf += thislen;
1514*4882a593Smuzhiyun }
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun ops->retlen = written;
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun return ret;
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun /**
1522*4882a593Smuzhiyun * onenand_write_oob_nolock - [INTERN] OneNAND write out-of-band
1523*4882a593Smuzhiyun * @param mtd MTD device structure
1524*4882a593Smuzhiyun * @param to offset to write to
1525*4882a593Smuzhiyun * @param len number of bytes to write
1526*4882a593Smuzhiyun * @param retlen pointer to variable to store the number of written bytes
1527*4882a593Smuzhiyun * @param buf the data to write
1528*4882a593Smuzhiyun * @param mode operation mode
1529*4882a593Smuzhiyun *
1530*4882a593Smuzhiyun * OneNAND write out-of-band
1531*4882a593Smuzhiyun */
onenand_write_oob_nolock(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)1532*4882a593Smuzhiyun static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to,
1533*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1536*4882a593Smuzhiyun int column, ret = 0, oobsize;
1537*4882a593Smuzhiyun int written = 0, oobcmd;
1538*4882a593Smuzhiyun u_char *oobbuf;
1539*4882a593Smuzhiyun size_t len = ops->ooblen;
1540*4882a593Smuzhiyun const u_char *buf = ops->oobbuf;
1541*4882a593Smuzhiyun unsigned int mode = ops->mode;
1542*4882a593Smuzhiyun
1543*4882a593Smuzhiyun to += ops->ooboffs;
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun pr_debug("onenand_write_oob_nolock: to = 0x%08x, len = %i\n",
1546*4882a593Smuzhiyun (unsigned int) to, (int) len);
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun /* Initialize retlen, in case of early exit */
1549*4882a593Smuzhiyun ops->oobretlen = 0;
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun if (mode == MTD_OPS_AUTO_OOB)
1552*4882a593Smuzhiyun oobsize = this->ecclayout->oobavail;
1553*4882a593Smuzhiyun else
1554*4882a593Smuzhiyun oobsize = mtd->oobsize;
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun column = to & (mtd->oobsize - 1);
1557*4882a593Smuzhiyun
1558*4882a593Smuzhiyun if (unlikely(column >= oobsize)) {
1559*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_oob_nolock: Attempted to start write outside oob\n");
1560*4882a593Smuzhiyun return -EINVAL;
1561*4882a593Smuzhiyun }
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun /* For compatibility with NAND: Do not allow write past end of page */
1564*4882a593Smuzhiyun if (unlikely(column + len > oobsize)) {
1565*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_oob_nolock: "
1566*4882a593Smuzhiyun "Attempt to write past end of page\n");
1567*4882a593Smuzhiyun return -EINVAL;
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun /* Do not allow reads past end of device */
1571*4882a593Smuzhiyun if (unlikely(to >= mtd->size ||
1572*4882a593Smuzhiyun column + len > ((mtd->size >> this->page_shift) -
1573*4882a593Smuzhiyun (to >> this->page_shift)) * oobsize)) {
1574*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_oob_nolock: Attempted to write past end of device\n");
1575*4882a593Smuzhiyun return -EINVAL;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun oobbuf = this->oob_buf;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun oobcmd = ONENAND_IS_4KB_PAGE(this) ?
1581*4882a593Smuzhiyun ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun /* Loop until all data write */
1584*4882a593Smuzhiyun while (written < len) {
1585*4882a593Smuzhiyun int thislen = min_t(int, oobsize, len - written);
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
1588*4882a593Smuzhiyun
1589*4882a593Smuzhiyun /* We send data to spare ram with oobsize
1590*4882a593Smuzhiyun * to prevent byte access */
1591*4882a593Smuzhiyun memset(oobbuf, 0xff, mtd->oobsize);
1592*4882a593Smuzhiyun if (mode == MTD_OPS_AUTO_OOB)
1593*4882a593Smuzhiyun onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
1594*4882a593Smuzhiyun else
1595*4882a593Smuzhiyun memcpy(oobbuf + column, buf, thislen);
1596*4882a593Smuzhiyun this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this)) {
1599*4882a593Smuzhiyun /* Set main area of DataRAM to 0xff*/
1600*4882a593Smuzhiyun memset(this->page_buf, 0xff, mtd->writesize);
1601*4882a593Smuzhiyun this->write_bufferram(mtd, 0, ONENAND_DATARAM,
1602*4882a593Smuzhiyun this->page_buf, 0, mtd->writesize);
1603*4882a593Smuzhiyun }
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun this->command(mtd, oobcmd, to, mtd->oobsize);
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun onenand_update_bufferram(mtd, to, 0);
1608*4882a593Smuzhiyun if (ONENAND_IS_2PLANE(this)) {
1609*4882a593Smuzhiyun ONENAND_SET_BUFFERRAM1(this);
1610*4882a593Smuzhiyun onenand_update_bufferram(mtd, to + this->writesize, 0);
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun ret = this->wait(mtd, FL_WRITING);
1614*4882a593Smuzhiyun if (ret) {
1615*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_oob_nolock: write failed %d\n", ret);
1616*4882a593Smuzhiyun break;
1617*4882a593Smuzhiyun }
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun ret = onenand_verify_oob(mtd, oobbuf, to);
1620*4882a593Smuzhiyun if (ret) {
1621*4882a593Smuzhiyun printk(KERN_ERR "onenand_write_oob_nolock: verify failed %d\n", ret);
1622*4882a593Smuzhiyun break;
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun
1625*4882a593Smuzhiyun written += thislen;
1626*4882a593Smuzhiyun if (written == len)
1627*4882a593Smuzhiyun break;
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun to += mtd->writesize;
1630*4882a593Smuzhiyun buf += thislen;
1631*4882a593Smuzhiyun column = 0;
1632*4882a593Smuzhiyun }
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun ops->oobretlen = written;
1635*4882a593Smuzhiyun
1636*4882a593Smuzhiyun return ret;
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun /**
1640*4882a593Smuzhiyun * onenand_write - [MTD Interface] compability function for onenand_write_ecc
1641*4882a593Smuzhiyun * @param mtd MTD device structure
1642*4882a593Smuzhiyun * @param to offset to write to
1643*4882a593Smuzhiyun * @param len number of bytes to write
1644*4882a593Smuzhiyun * @param retlen pointer to variable to store the number of written bytes
1645*4882a593Smuzhiyun * @param buf the data to write
1646*4882a593Smuzhiyun *
1647*4882a593Smuzhiyun * Write with ECC
1648*4882a593Smuzhiyun */
onenand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1649*4882a593Smuzhiyun int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
1650*4882a593Smuzhiyun size_t * retlen, const u_char * buf)
1651*4882a593Smuzhiyun {
1652*4882a593Smuzhiyun struct mtd_oob_ops ops = {
1653*4882a593Smuzhiyun .len = len,
1654*4882a593Smuzhiyun .ooblen = 0,
1655*4882a593Smuzhiyun .datbuf = (u_char *) buf,
1656*4882a593Smuzhiyun .oobbuf = NULL,
1657*4882a593Smuzhiyun };
1658*4882a593Smuzhiyun int ret;
1659*4882a593Smuzhiyun
1660*4882a593Smuzhiyun onenand_get_device(mtd, FL_WRITING);
1661*4882a593Smuzhiyun ret = onenand_write_ops_nolock(mtd, to, &ops);
1662*4882a593Smuzhiyun onenand_release_device(mtd);
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun *retlen = ops.retlen;
1665*4882a593Smuzhiyun return ret;
1666*4882a593Smuzhiyun }
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun /**
1669*4882a593Smuzhiyun * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
1670*4882a593Smuzhiyun * @param mtd MTD device structure
1671*4882a593Smuzhiyun * @param to offset to write to
1672*4882a593Smuzhiyun * @param ops oob operation description structure
1673*4882a593Smuzhiyun *
1674*4882a593Smuzhiyun * OneNAND write main and/or out-of-band
1675*4882a593Smuzhiyun */
onenand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)1676*4882a593Smuzhiyun int onenand_write_oob(struct mtd_info *mtd, loff_t to,
1677*4882a593Smuzhiyun struct mtd_oob_ops *ops)
1678*4882a593Smuzhiyun {
1679*4882a593Smuzhiyun int ret;
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun switch (ops->mode) {
1682*4882a593Smuzhiyun case MTD_OPS_PLACE_OOB:
1683*4882a593Smuzhiyun case MTD_OPS_AUTO_OOB:
1684*4882a593Smuzhiyun break;
1685*4882a593Smuzhiyun case MTD_OPS_RAW:
1686*4882a593Smuzhiyun /* Not implemented yet */
1687*4882a593Smuzhiyun default:
1688*4882a593Smuzhiyun return -EINVAL;
1689*4882a593Smuzhiyun }
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun onenand_get_device(mtd, FL_WRITING);
1692*4882a593Smuzhiyun if (ops->datbuf)
1693*4882a593Smuzhiyun ret = onenand_write_ops_nolock(mtd, to, ops);
1694*4882a593Smuzhiyun else
1695*4882a593Smuzhiyun ret = onenand_write_oob_nolock(mtd, to, ops);
1696*4882a593Smuzhiyun onenand_release_device(mtd);
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun return ret;
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun }
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun /**
1703*4882a593Smuzhiyun * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
1704*4882a593Smuzhiyun * @param mtd MTD device structure
1705*4882a593Smuzhiyun * @param ofs offset from device start
1706*4882a593Smuzhiyun * @param allowbbt 1, if its allowed to access the bbt area
1707*4882a593Smuzhiyun *
1708*4882a593Smuzhiyun * Check, if the block is bad, Either by reading the bad block table or
1709*4882a593Smuzhiyun * calling of the scan function.
1710*4882a593Smuzhiyun */
onenand_block_isbad_nolock(struct mtd_info * mtd,loff_t ofs,int allowbbt)1711*4882a593Smuzhiyun static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
1712*4882a593Smuzhiyun {
1713*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1714*4882a593Smuzhiyun struct bbm_info *bbm = this->bbm;
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun /* Return info from the table */
1717*4882a593Smuzhiyun return bbm->isbad_bbt(mtd, ofs, allowbbt);
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun /**
1722*4882a593Smuzhiyun * onenand_erase - [MTD Interface] erase block(s)
1723*4882a593Smuzhiyun * @param mtd MTD device structure
1724*4882a593Smuzhiyun * @param instr erase instruction
1725*4882a593Smuzhiyun *
1726*4882a593Smuzhiyun * Erase one ore more blocks
1727*4882a593Smuzhiyun */
onenand_erase(struct mtd_info * mtd,struct erase_info * instr)1728*4882a593Smuzhiyun int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
1729*4882a593Smuzhiyun {
1730*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1731*4882a593Smuzhiyun unsigned int block_size;
1732*4882a593Smuzhiyun loff_t addr = instr->addr;
1733*4882a593Smuzhiyun unsigned int len = instr->len;
1734*4882a593Smuzhiyun int ret = 0, i;
1735*4882a593Smuzhiyun struct mtd_erase_region_info *region = NULL;
1736*4882a593Smuzhiyun unsigned int region_end = 0;
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun pr_debug("onenand_erase: start = 0x%08x, len = %i\n",
1739*4882a593Smuzhiyun (unsigned int) addr, len);
1740*4882a593Smuzhiyun
1741*4882a593Smuzhiyun if (FLEXONENAND(this)) {
1742*4882a593Smuzhiyun /* Find the eraseregion of this address */
1743*4882a593Smuzhiyun i = flexonenand_region(mtd, addr);
1744*4882a593Smuzhiyun region = &mtd->eraseregions[i];
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun block_size = region->erasesize;
1747*4882a593Smuzhiyun region_end = region->offset
1748*4882a593Smuzhiyun + region->erasesize * region->numblocks;
1749*4882a593Smuzhiyun
1750*4882a593Smuzhiyun /* Start address within region must align on block boundary.
1751*4882a593Smuzhiyun * Erase region's start offset is always block start address.
1752*4882a593Smuzhiyun */
1753*4882a593Smuzhiyun if (unlikely((addr - region->offset) & (block_size - 1))) {
1754*4882a593Smuzhiyun pr_debug("onenand_erase:" " Unaligned address\n");
1755*4882a593Smuzhiyun return -EINVAL;
1756*4882a593Smuzhiyun }
1757*4882a593Smuzhiyun } else {
1758*4882a593Smuzhiyun block_size = 1 << this->erase_shift;
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun /* Start address must align on block boundary */
1761*4882a593Smuzhiyun if (unlikely(addr & (block_size - 1))) {
1762*4882a593Smuzhiyun pr_debug("onenand_erase:" "Unaligned address\n");
1763*4882a593Smuzhiyun return -EINVAL;
1764*4882a593Smuzhiyun }
1765*4882a593Smuzhiyun }
1766*4882a593Smuzhiyun
1767*4882a593Smuzhiyun /* Length must align on block boundary */
1768*4882a593Smuzhiyun if (unlikely(len & (block_size - 1))) {
1769*4882a593Smuzhiyun pr_debug("onenand_erase: Length not block aligned\n");
1770*4882a593Smuzhiyun return -EINVAL;
1771*4882a593Smuzhiyun }
1772*4882a593Smuzhiyun
1773*4882a593Smuzhiyun /* Grab the lock and see if the device is available */
1774*4882a593Smuzhiyun onenand_get_device(mtd, FL_ERASING);
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun /* Loop throught the pages */
1777*4882a593Smuzhiyun instr->state = MTD_ERASING;
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun while (len) {
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun /* Check if we have a bad block, we do not erase bad blocks */
1782*4882a593Smuzhiyun if (instr->priv == 0 && onenand_block_isbad_nolock(mtd, addr, 0)) {
1783*4882a593Smuzhiyun printk(KERN_WARNING "onenand_erase: attempt to erase"
1784*4882a593Smuzhiyun " a bad block at addr 0x%08x\n",
1785*4882a593Smuzhiyun (unsigned int) addr);
1786*4882a593Smuzhiyun instr->state = MTD_ERASE_FAILED;
1787*4882a593Smuzhiyun goto erase_exit;
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun onenand_invalidate_bufferram(mtd, addr, block_size);
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun ret = this->wait(mtd, FL_ERASING);
1795*4882a593Smuzhiyun /* Check, if it is write protected */
1796*4882a593Smuzhiyun if (ret) {
1797*4882a593Smuzhiyun if (ret == -EPERM)
1798*4882a593Smuzhiyun pr_debug("onenand_erase: "
1799*4882a593Smuzhiyun "Device is write protected!!!\n");
1800*4882a593Smuzhiyun else
1801*4882a593Smuzhiyun pr_debug("onenand_erase: "
1802*4882a593Smuzhiyun "Failed erase, block %d\n",
1803*4882a593Smuzhiyun onenand_block(this, addr));
1804*4882a593Smuzhiyun instr->state = MTD_ERASE_FAILED;
1805*4882a593Smuzhiyun instr->fail_addr = addr;
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun goto erase_exit;
1808*4882a593Smuzhiyun }
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun len -= block_size;
1811*4882a593Smuzhiyun addr += block_size;
1812*4882a593Smuzhiyun
1813*4882a593Smuzhiyun if (addr == region_end) {
1814*4882a593Smuzhiyun if (!len)
1815*4882a593Smuzhiyun break;
1816*4882a593Smuzhiyun region++;
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun block_size = region->erasesize;
1819*4882a593Smuzhiyun region_end = region->offset
1820*4882a593Smuzhiyun + region->erasesize * region->numblocks;
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun if (len & (block_size - 1)) {
1823*4882a593Smuzhiyun /* This has been checked at MTD
1824*4882a593Smuzhiyun * partitioning level. */
1825*4882a593Smuzhiyun printk("onenand_erase: Unaligned address\n");
1826*4882a593Smuzhiyun goto erase_exit;
1827*4882a593Smuzhiyun }
1828*4882a593Smuzhiyun }
1829*4882a593Smuzhiyun }
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun instr->state = MTD_ERASE_DONE;
1832*4882a593Smuzhiyun
1833*4882a593Smuzhiyun erase_exit:
1834*4882a593Smuzhiyun
1835*4882a593Smuzhiyun ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1836*4882a593Smuzhiyun /* Do call back function */
1837*4882a593Smuzhiyun if (!ret)
1838*4882a593Smuzhiyun mtd_erase_callback(instr);
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun /* Deselect and wake up anyone waiting on the device */
1841*4882a593Smuzhiyun onenand_release_device(mtd);
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun return ret;
1844*4882a593Smuzhiyun }
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun /**
1847*4882a593Smuzhiyun * onenand_sync - [MTD Interface] sync
1848*4882a593Smuzhiyun * @param mtd MTD device structure
1849*4882a593Smuzhiyun *
1850*4882a593Smuzhiyun * Sync is actually a wait for chip ready function
1851*4882a593Smuzhiyun */
onenand_sync(struct mtd_info * mtd)1852*4882a593Smuzhiyun void onenand_sync(struct mtd_info *mtd)
1853*4882a593Smuzhiyun {
1854*4882a593Smuzhiyun pr_debug("onenand_sync: called\n");
1855*4882a593Smuzhiyun
1856*4882a593Smuzhiyun /* Grab the lock and see if the device is available */
1857*4882a593Smuzhiyun onenand_get_device(mtd, FL_SYNCING);
1858*4882a593Smuzhiyun
1859*4882a593Smuzhiyun /* Release it and go back */
1860*4882a593Smuzhiyun onenand_release_device(mtd);
1861*4882a593Smuzhiyun }
1862*4882a593Smuzhiyun
1863*4882a593Smuzhiyun /**
1864*4882a593Smuzhiyun * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
1865*4882a593Smuzhiyun * @param mtd MTD device structure
1866*4882a593Smuzhiyun * @param ofs offset relative to mtd start
1867*4882a593Smuzhiyun *
1868*4882a593Smuzhiyun * Check whether the block is bad
1869*4882a593Smuzhiyun */
onenand_block_isbad(struct mtd_info * mtd,loff_t ofs)1870*4882a593Smuzhiyun int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
1871*4882a593Smuzhiyun {
1872*4882a593Smuzhiyun int ret;
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun /* Check for invalid offset */
1875*4882a593Smuzhiyun if (ofs > mtd->size)
1876*4882a593Smuzhiyun return -EINVAL;
1877*4882a593Smuzhiyun
1878*4882a593Smuzhiyun onenand_get_device(mtd, FL_READING);
1879*4882a593Smuzhiyun ret = onenand_block_isbad_nolock(mtd,ofs, 0);
1880*4882a593Smuzhiyun onenand_release_device(mtd);
1881*4882a593Smuzhiyun return ret;
1882*4882a593Smuzhiyun }
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun /**
1885*4882a593Smuzhiyun * onenand_default_block_markbad - [DEFAULT] mark a block bad
1886*4882a593Smuzhiyun * @param mtd MTD device structure
1887*4882a593Smuzhiyun * @param ofs offset from device start
1888*4882a593Smuzhiyun *
1889*4882a593Smuzhiyun * This is the default implementation, which can be overridden by
1890*4882a593Smuzhiyun * a hardware specific driver.
1891*4882a593Smuzhiyun */
onenand_default_block_markbad(struct mtd_info * mtd,loff_t ofs)1892*4882a593Smuzhiyun static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
1893*4882a593Smuzhiyun {
1894*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1895*4882a593Smuzhiyun struct bbm_info *bbm = this->bbm;
1896*4882a593Smuzhiyun u_char buf[2] = {0, 0};
1897*4882a593Smuzhiyun struct mtd_oob_ops ops = {
1898*4882a593Smuzhiyun .mode = MTD_OPS_PLACE_OOB,
1899*4882a593Smuzhiyun .ooblen = 2,
1900*4882a593Smuzhiyun .oobbuf = buf,
1901*4882a593Smuzhiyun .ooboffs = 0,
1902*4882a593Smuzhiyun };
1903*4882a593Smuzhiyun int block;
1904*4882a593Smuzhiyun
1905*4882a593Smuzhiyun /* Get block number */
1906*4882a593Smuzhiyun block = onenand_block(this, ofs);
1907*4882a593Smuzhiyun if (bbm->bbt)
1908*4882a593Smuzhiyun bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1909*4882a593Smuzhiyun
1910*4882a593Smuzhiyun /* We write two bytes, so we dont have to mess with 16 bit access */
1911*4882a593Smuzhiyun ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
1912*4882a593Smuzhiyun return onenand_write_oob_nolock(mtd, ofs, &ops);
1913*4882a593Smuzhiyun }
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun /**
1916*4882a593Smuzhiyun * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
1917*4882a593Smuzhiyun * @param mtd MTD device structure
1918*4882a593Smuzhiyun * @param ofs offset relative to mtd start
1919*4882a593Smuzhiyun *
1920*4882a593Smuzhiyun * Mark the block as bad
1921*4882a593Smuzhiyun */
onenand_block_markbad(struct mtd_info * mtd,loff_t ofs)1922*4882a593Smuzhiyun int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1923*4882a593Smuzhiyun {
1924*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1925*4882a593Smuzhiyun int ret;
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun ret = onenand_block_isbad(mtd, ofs);
1928*4882a593Smuzhiyun if (ret) {
1929*4882a593Smuzhiyun /* If it was bad already, return success and do nothing */
1930*4882a593Smuzhiyun if (ret > 0)
1931*4882a593Smuzhiyun return 0;
1932*4882a593Smuzhiyun return ret;
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun onenand_get_device(mtd, FL_WRITING);
1936*4882a593Smuzhiyun ret = this->block_markbad(mtd, ofs);
1937*4882a593Smuzhiyun onenand_release_device(mtd);
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun return ret;
1940*4882a593Smuzhiyun }
1941*4882a593Smuzhiyun
1942*4882a593Smuzhiyun /**
1943*4882a593Smuzhiyun * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
1944*4882a593Smuzhiyun * @param mtd MTD device structure
1945*4882a593Smuzhiyun * @param ofs offset relative to mtd start
1946*4882a593Smuzhiyun * @param len number of bytes to lock or unlock
1947*4882a593Smuzhiyun * @param cmd lock or unlock command
1948*4882a593Smuzhiyun *
1949*4882a593Smuzhiyun * Lock or unlock one or more blocks
1950*4882a593Smuzhiyun */
onenand_do_lock_cmd(struct mtd_info * mtd,loff_t ofs,size_t len,int cmd)1951*4882a593Smuzhiyun static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
1952*4882a593Smuzhiyun {
1953*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
1954*4882a593Smuzhiyun int start, end, block, value, status;
1955*4882a593Smuzhiyun
1956*4882a593Smuzhiyun start = onenand_block(this, ofs);
1957*4882a593Smuzhiyun end = onenand_block(this, ofs + len);
1958*4882a593Smuzhiyun
1959*4882a593Smuzhiyun /* Continuous lock scheme */
1960*4882a593Smuzhiyun if (this->options & ONENAND_HAS_CONT_LOCK) {
1961*4882a593Smuzhiyun /* Set start block address */
1962*4882a593Smuzhiyun this->write_word(start,
1963*4882a593Smuzhiyun this->base + ONENAND_REG_START_BLOCK_ADDRESS);
1964*4882a593Smuzhiyun /* Set end block address */
1965*4882a593Smuzhiyun this->write_word(end - 1,
1966*4882a593Smuzhiyun this->base + ONENAND_REG_END_BLOCK_ADDRESS);
1967*4882a593Smuzhiyun /* Write unlock command */
1968*4882a593Smuzhiyun this->command(mtd, cmd, 0, 0);
1969*4882a593Smuzhiyun
1970*4882a593Smuzhiyun /* There's no return value */
1971*4882a593Smuzhiyun this->wait(mtd, FL_UNLOCKING);
1972*4882a593Smuzhiyun
1973*4882a593Smuzhiyun /* Sanity check */
1974*4882a593Smuzhiyun while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
1975*4882a593Smuzhiyun & ONENAND_CTRL_ONGO)
1976*4882a593Smuzhiyun continue;
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun /* Check lock status */
1979*4882a593Smuzhiyun status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
1980*4882a593Smuzhiyun if (!(status & ONENAND_WP_US))
1981*4882a593Smuzhiyun printk(KERN_ERR "wp status = 0x%x\n", status);
1982*4882a593Smuzhiyun
1983*4882a593Smuzhiyun return 0;
1984*4882a593Smuzhiyun }
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun /* Block lock scheme */
1987*4882a593Smuzhiyun for (block = start; block < end; block++) {
1988*4882a593Smuzhiyun /* Set block address */
1989*4882a593Smuzhiyun value = onenand_block_address(this, block);
1990*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
1991*4882a593Smuzhiyun /* Select DataRAM for DDP */
1992*4882a593Smuzhiyun value = onenand_bufferram_address(this, block);
1993*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun /* Set start block address */
1996*4882a593Smuzhiyun this->write_word(block,
1997*4882a593Smuzhiyun this->base + ONENAND_REG_START_BLOCK_ADDRESS);
1998*4882a593Smuzhiyun /* Write unlock command */
1999*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
2000*4882a593Smuzhiyun
2001*4882a593Smuzhiyun /* There's no return value */
2002*4882a593Smuzhiyun this->wait(mtd, FL_UNLOCKING);
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun /* Sanity check */
2005*4882a593Smuzhiyun while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2006*4882a593Smuzhiyun & ONENAND_CTRL_ONGO)
2007*4882a593Smuzhiyun continue;
2008*4882a593Smuzhiyun
2009*4882a593Smuzhiyun /* Check lock status */
2010*4882a593Smuzhiyun status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
2011*4882a593Smuzhiyun if (!(status & ONENAND_WP_US))
2012*4882a593Smuzhiyun printk(KERN_ERR "block = %d, wp status = 0x%x\n",
2013*4882a593Smuzhiyun block, status);
2014*4882a593Smuzhiyun }
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun return 0;
2017*4882a593Smuzhiyun }
2018*4882a593Smuzhiyun
2019*4882a593Smuzhiyun #ifdef ONENAND_LINUX
2020*4882a593Smuzhiyun /**
2021*4882a593Smuzhiyun * onenand_lock - [MTD Interface] Lock block(s)
2022*4882a593Smuzhiyun * @param mtd MTD device structure
2023*4882a593Smuzhiyun * @param ofs offset relative to mtd start
2024*4882a593Smuzhiyun * @param len number of bytes to unlock
2025*4882a593Smuzhiyun *
2026*4882a593Smuzhiyun * Lock one or more blocks
2027*4882a593Smuzhiyun */
onenand_lock(struct mtd_info * mtd,loff_t ofs,size_t len)2028*4882a593Smuzhiyun static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
2029*4882a593Smuzhiyun {
2030*4882a593Smuzhiyun int ret;
2031*4882a593Smuzhiyun
2032*4882a593Smuzhiyun onenand_get_device(mtd, FL_LOCKING);
2033*4882a593Smuzhiyun ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
2034*4882a593Smuzhiyun onenand_release_device(mtd);
2035*4882a593Smuzhiyun return ret;
2036*4882a593Smuzhiyun }
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun /**
2039*4882a593Smuzhiyun * onenand_unlock - [MTD Interface] Unlock block(s)
2040*4882a593Smuzhiyun * @param mtd MTD device structure
2041*4882a593Smuzhiyun * @param ofs offset relative to mtd start
2042*4882a593Smuzhiyun * @param len number of bytes to unlock
2043*4882a593Smuzhiyun *
2044*4882a593Smuzhiyun * Unlock one or more blocks
2045*4882a593Smuzhiyun */
onenand_unlock(struct mtd_info * mtd,loff_t ofs,size_t len)2046*4882a593Smuzhiyun static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
2047*4882a593Smuzhiyun {
2048*4882a593Smuzhiyun int ret;
2049*4882a593Smuzhiyun
2050*4882a593Smuzhiyun onenand_get_device(mtd, FL_LOCKING);
2051*4882a593Smuzhiyun ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2052*4882a593Smuzhiyun onenand_release_device(mtd);
2053*4882a593Smuzhiyun return ret;
2054*4882a593Smuzhiyun }
2055*4882a593Smuzhiyun #endif
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun /**
2058*4882a593Smuzhiyun * onenand_check_lock_status - [OneNAND Interface] Check lock status
2059*4882a593Smuzhiyun * @param this onenand chip data structure
2060*4882a593Smuzhiyun *
2061*4882a593Smuzhiyun * Check lock status
2062*4882a593Smuzhiyun */
onenand_check_lock_status(struct onenand_chip * this)2063*4882a593Smuzhiyun static int onenand_check_lock_status(struct onenand_chip *this)
2064*4882a593Smuzhiyun {
2065*4882a593Smuzhiyun unsigned int value, block, status;
2066*4882a593Smuzhiyun unsigned int end;
2067*4882a593Smuzhiyun
2068*4882a593Smuzhiyun end = this->chipsize >> this->erase_shift;
2069*4882a593Smuzhiyun for (block = 0; block < end; block++) {
2070*4882a593Smuzhiyun /* Set block address */
2071*4882a593Smuzhiyun value = onenand_block_address(this, block);
2072*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2073*4882a593Smuzhiyun /* Select DataRAM for DDP */
2074*4882a593Smuzhiyun value = onenand_bufferram_address(this, block);
2075*4882a593Smuzhiyun this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
2076*4882a593Smuzhiyun /* Set start block address */
2077*4882a593Smuzhiyun this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2078*4882a593Smuzhiyun
2079*4882a593Smuzhiyun /* Check lock status */
2080*4882a593Smuzhiyun status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
2081*4882a593Smuzhiyun if (!(status & ONENAND_WP_US)) {
2082*4882a593Smuzhiyun printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
2083*4882a593Smuzhiyun return 0;
2084*4882a593Smuzhiyun }
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun
2087*4882a593Smuzhiyun return 1;
2088*4882a593Smuzhiyun }
2089*4882a593Smuzhiyun
2090*4882a593Smuzhiyun /**
2091*4882a593Smuzhiyun * onenand_unlock_all - [OneNAND Interface] unlock all blocks
2092*4882a593Smuzhiyun * @param mtd MTD device structure
2093*4882a593Smuzhiyun *
2094*4882a593Smuzhiyun * Unlock all blocks
2095*4882a593Smuzhiyun */
onenand_unlock_all(struct mtd_info * mtd)2096*4882a593Smuzhiyun static void onenand_unlock_all(struct mtd_info *mtd)
2097*4882a593Smuzhiyun {
2098*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2099*4882a593Smuzhiyun loff_t ofs = 0;
2100*4882a593Smuzhiyun size_t len = mtd->size;
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun if (this->options & ONENAND_HAS_UNLOCK_ALL) {
2103*4882a593Smuzhiyun /* Set start block address */
2104*4882a593Smuzhiyun this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2105*4882a593Smuzhiyun /* Write unlock command */
2106*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
2107*4882a593Smuzhiyun
2108*4882a593Smuzhiyun /* There's no return value */
2109*4882a593Smuzhiyun this->wait(mtd, FL_LOCKING);
2110*4882a593Smuzhiyun
2111*4882a593Smuzhiyun /* Sanity check */
2112*4882a593Smuzhiyun while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2113*4882a593Smuzhiyun & ONENAND_CTRL_ONGO)
2114*4882a593Smuzhiyun continue;
2115*4882a593Smuzhiyun
2116*4882a593Smuzhiyun /* Check lock status */
2117*4882a593Smuzhiyun if (onenand_check_lock_status(this))
2118*4882a593Smuzhiyun return;
2119*4882a593Smuzhiyun
2120*4882a593Smuzhiyun /* Workaround for all block unlock in DDP */
2121*4882a593Smuzhiyun if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
2122*4882a593Smuzhiyun /* All blocks on another chip */
2123*4882a593Smuzhiyun ofs = this->chipsize >> 1;
2124*4882a593Smuzhiyun len = this->chipsize >> 1;
2125*4882a593Smuzhiyun }
2126*4882a593Smuzhiyun }
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2129*4882a593Smuzhiyun }
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun
2132*4882a593Smuzhiyun /**
2133*4882a593Smuzhiyun * onenand_check_features - Check and set OneNAND features
2134*4882a593Smuzhiyun * @param mtd MTD data structure
2135*4882a593Smuzhiyun *
2136*4882a593Smuzhiyun * Check and set OneNAND features
2137*4882a593Smuzhiyun * - lock scheme
2138*4882a593Smuzhiyun * - two plane
2139*4882a593Smuzhiyun */
onenand_check_features(struct mtd_info * mtd)2140*4882a593Smuzhiyun static void onenand_check_features(struct mtd_info *mtd)
2141*4882a593Smuzhiyun {
2142*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2143*4882a593Smuzhiyun unsigned int density, process;
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun /* Lock scheme depends on density and process */
2146*4882a593Smuzhiyun density = onenand_get_density(this->device_id);
2147*4882a593Smuzhiyun process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
2148*4882a593Smuzhiyun
2149*4882a593Smuzhiyun /* Lock scheme */
2150*4882a593Smuzhiyun switch (density) {
2151*4882a593Smuzhiyun case ONENAND_DEVICE_DENSITY_4Gb:
2152*4882a593Smuzhiyun if (ONENAND_IS_DDP(this))
2153*4882a593Smuzhiyun this->options |= ONENAND_HAS_2PLANE;
2154*4882a593Smuzhiyun else
2155*4882a593Smuzhiyun this->options |= ONENAND_HAS_4KB_PAGE;
2156*4882a593Smuzhiyun
2157*4882a593Smuzhiyun case ONENAND_DEVICE_DENSITY_2Gb:
2158*4882a593Smuzhiyun /* 2Gb DDP don't have 2 plane */
2159*4882a593Smuzhiyun if (!ONENAND_IS_DDP(this))
2160*4882a593Smuzhiyun this->options |= ONENAND_HAS_2PLANE;
2161*4882a593Smuzhiyun this->options |= ONENAND_HAS_UNLOCK_ALL;
2162*4882a593Smuzhiyun
2163*4882a593Smuzhiyun case ONENAND_DEVICE_DENSITY_1Gb:
2164*4882a593Smuzhiyun /* A-Die has all block unlock */
2165*4882a593Smuzhiyun if (process)
2166*4882a593Smuzhiyun this->options |= ONENAND_HAS_UNLOCK_ALL;
2167*4882a593Smuzhiyun break;
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun default:
2170*4882a593Smuzhiyun /* Some OneNAND has continuous lock scheme */
2171*4882a593Smuzhiyun if (!process)
2172*4882a593Smuzhiyun this->options |= ONENAND_HAS_CONT_LOCK;
2173*4882a593Smuzhiyun break;
2174*4882a593Smuzhiyun }
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun if (ONENAND_IS_MLC(this))
2177*4882a593Smuzhiyun this->options |= ONENAND_HAS_4KB_PAGE;
2178*4882a593Smuzhiyun
2179*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this))
2180*4882a593Smuzhiyun this->options &= ~ONENAND_HAS_2PLANE;
2181*4882a593Smuzhiyun
2182*4882a593Smuzhiyun if (FLEXONENAND(this)) {
2183*4882a593Smuzhiyun this->options &= ~ONENAND_HAS_CONT_LOCK;
2184*4882a593Smuzhiyun this->options |= ONENAND_HAS_UNLOCK_ALL;
2185*4882a593Smuzhiyun }
2186*4882a593Smuzhiyun
2187*4882a593Smuzhiyun if (this->options & ONENAND_HAS_CONT_LOCK)
2188*4882a593Smuzhiyun printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
2189*4882a593Smuzhiyun if (this->options & ONENAND_HAS_UNLOCK_ALL)
2190*4882a593Smuzhiyun printk(KERN_DEBUG "Chip support all block unlock\n");
2191*4882a593Smuzhiyun if (this->options & ONENAND_HAS_2PLANE)
2192*4882a593Smuzhiyun printk(KERN_DEBUG "Chip has 2 plane\n");
2193*4882a593Smuzhiyun if (this->options & ONENAND_HAS_4KB_PAGE)
2194*4882a593Smuzhiyun printk(KERN_DEBUG "Chip has 4KiB pagesize\n");
2195*4882a593Smuzhiyun
2196*4882a593Smuzhiyun }
2197*4882a593Smuzhiyun
2198*4882a593Smuzhiyun /**
2199*4882a593Smuzhiyun * onenand_print_device_info - Print device ID
2200*4882a593Smuzhiyun * @param device device ID
2201*4882a593Smuzhiyun *
2202*4882a593Smuzhiyun * Print device ID
2203*4882a593Smuzhiyun */
onenand_print_device_info(int device,int version)2204*4882a593Smuzhiyun char *onenand_print_device_info(int device, int version)
2205*4882a593Smuzhiyun {
2206*4882a593Smuzhiyun int vcc, demuxed, ddp, density, flexonenand;
2207*4882a593Smuzhiyun char *dev_info = malloc(80);
2208*4882a593Smuzhiyun char *p = dev_info;
2209*4882a593Smuzhiyun
2210*4882a593Smuzhiyun vcc = device & ONENAND_DEVICE_VCC_MASK;
2211*4882a593Smuzhiyun demuxed = device & ONENAND_DEVICE_IS_DEMUX;
2212*4882a593Smuzhiyun ddp = device & ONENAND_DEVICE_IS_DDP;
2213*4882a593Smuzhiyun density = onenand_get_density(device);
2214*4882a593Smuzhiyun flexonenand = device & DEVICE_IS_FLEXONENAND;
2215*4882a593Smuzhiyun p += sprintf(dev_info, "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)",
2216*4882a593Smuzhiyun demuxed ? "" : "Muxed ",
2217*4882a593Smuzhiyun flexonenand ? "Flex-" : "",
2218*4882a593Smuzhiyun ddp ? "(DDP)" : "",
2219*4882a593Smuzhiyun (16 << density), vcc ? "2.65/3.3" : "1.8", device);
2220*4882a593Smuzhiyun
2221*4882a593Smuzhiyun sprintf(p, "\nOneNAND version = 0x%04x", version);
2222*4882a593Smuzhiyun printk("%s\n", dev_info);
2223*4882a593Smuzhiyun
2224*4882a593Smuzhiyun return dev_info;
2225*4882a593Smuzhiyun }
2226*4882a593Smuzhiyun
2227*4882a593Smuzhiyun static const struct onenand_manufacturers onenand_manuf_ids[] = {
2228*4882a593Smuzhiyun {ONENAND_MFR_NUMONYX, "Numonyx"},
2229*4882a593Smuzhiyun {ONENAND_MFR_SAMSUNG, "Samsung"},
2230*4882a593Smuzhiyun };
2231*4882a593Smuzhiyun
2232*4882a593Smuzhiyun /**
2233*4882a593Smuzhiyun * onenand_check_maf - Check manufacturer ID
2234*4882a593Smuzhiyun * @param manuf manufacturer ID
2235*4882a593Smuzhiyun *
2236*4882a593Smuzhiyun * Check manufacturer ID
2237*4882a593Smuzhiyun */
onenand_check_maf(int manuf)2238*4882a593Smuzhiyun static int onenand_check_maf(int manuf)
2239*4882a593Smuzhiyun {
2240*4882a593Smuzhiyun int size = ARRAY_SIZE(onenand_manuf_ids);
2241*4882a593Smuzhiyun int i;
2242*4882a593Smuzhiyun #ifdef ONENAND_DEBUG
2243*4882a593Smuzhiyun char *name;
2244*4882a593Smuzhiyun #endif
2245*4882a593Smuzhiyun
2246*4882a593Smuzhiyun for (i = 0; i < size; i++)
2247*4882a593Smuzhiyun if (manuf == onenand_manuf_ids[i].id)
2248*4882a593Smuzhiyun break;
2249*4882a593Smuzhiyun
2250*4882a593Smuzhiyun #ifdef ONENAND_DEBUG
2251*4882a593Smuzhiyun if (i < size)
2252*4882a593Smuzhiyun name = onenand_manuf_ids[i].name;
2253*4882a593Smuzhiyun else
2254*4882a593Smuzhiyun name = "Unknown";
2255*4882a593Smuzhiyun
2256*4882a593Smuzhiyun printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
2257*4882a593Smuzhiyun #endif
2258*4882a593Smuzhiyun
2259*4882a593Smuzhiyun return i == size;
2260*4882a593Smuzhiyun }
2261*4882a593Smuzhiyun
2262*4882a593Smuzhiyun /**
2263*4882a593Smuzhiyun * flexonenand_get_boundary - Reads the SLC boundary
2264*4882a593Smuzhiyun * @param onenand_info - onenand info structure
2265*4882a593Smuzhiyun *
2266*4882a593Smuzhiyun * Fill up boundary[] field in onenand_chip
2267*4882a593Smuzhiyun **/
flexonenand_get_boundary(struct mtd_info * mtd)2268*4882a593Smuzhiyun static int flexonenand_get_boundary(struct mtd_info *mtd)
2269*4882a593Smuzhiyun {
2270*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2271*4882a593Smuzhiyun unsigned int die, bdry;
2272*4882a593Smuzhiyun int syscfg, locked;
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun /* Disable ECC */
2275*4882a593Smuzhiyun syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
2276*4882a593Smuzhiyun this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
2277*4882a593Smuzhiyun
2278*4882a593Smuzhiyun for (die = 0; die < this->dies; die++) {
2279*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
2280*4882a593Smuzhiyun this->wait(mtd, FL_SYNCING);
2281*4882a593Smuzhiyun
2282*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
2283*4882a593Smuzhiyun this->wait(mtd, FL_READING);
2284*4882a593Smuzhiyun
2285*4882a593Smuzhiyun bdry = this->read_word(this->base + ONENAND_DATARAM);
2286*4882a593Smuzhiyun if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
2287*4882a593Smuzhiyun locked = 0;
2288*4882a593Smuzhiyun else
2289*4882a593Smuzhiyun locked = 1;
2290*4882a593Smuzhiyun this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
2291*4882a593Smuzhiyun
2292*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2293*4882a593Smuzhiyun this->wait(mtd, FL_RESETING);
2294*4882a593Smuzhiyun
2295*4882a593Smuzhiyun printk(KERN_INFO "Die %d boundary: %d%s\n", die,
2296*4882a593Smuzhiyun this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
2297*4882a593Smuzhiyun }
2298*4882a593Smuzhiyun
2299*4882a593Smuzhiyun /* Enable ECC */
2300*4882a593Smuzhiyun this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
2301*4882a593Smuzhiyun return 0;
2302*4882a593Smuzhiyun }
2303*4882a593Smuzhiyun
2304*4882a593Smuzhiyun /**
2305*4882a593Smuzhiyun * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
2306*4882a593Smuzhiyun * boundary[], diesize[], mtd->size, mtd->erasesize,
2307*4882a593Smuzhiyun * mtd->eraseregions
2308*4882a593Smuzhiyun * @param mtd - MTD device structure
2309*4882a593Smuzhiyun */
flexonenand_get_size(struct mtd_info * mtd)2310*4882a593Smuzhiyun static void flexonenand_get_size(struct mtd_info *mtd)
2311*4882a593Smuzhiyun {
2312*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2313*4882a593Smuzhiyun int die, i, eraseshift, density;
2314*4882a593Smuzhiyun int blksperdie, maxbdry;
2315*4882a593Smuzhiyun loff_t ofs;
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun density = onenand_get_density(this->device_id);
2318*4882a593Smuzhiyun blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
2319*4882a593Smuzhiyun blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
2320*4882a593Smuzhiyun maxbdry = blksperdie - 1;
2321*4882a593Smuzhiyun eraseshift = this->erase_shift - 1;
2322*4882a593Smuzhiyun
2323*4882a593Smuzhiyun mtd->numeraseregions = this->dies << 1;
2324*4882a593Smuzhiyun
2325*4882a593Smuzhiyun /* This fills up the device boundary */
2326*4882a593Smuzhiyun flexonenand_get_boundary(mtd);
2327*4882a593Smuzhiyun die = 0;
2328*4882a593Smuzhiyun ofs = 0;
2329*4882a593Smuzhiyun i = -1;
2330*4882a593Smuzhiyun for (; die < this->dies; die++) {
2331*4882a593Smuzhiyun if (!die || this->boundary[die-1] != maxbdry) {
2332*4882a593Smuzhiyun i++;
2333*4882a593Smuzhiyun mtd->eraseregions[i].offset = ofs;
2334*4882a593Smuzhiyun mtd->eraseregions[i].erasesize = 1 << eraseshift;
2335*4882a593Smuzhiyun mtd->eraseregions[i].numblocks =
2336*4882a593Smuzhiyun this->boundary[die] + 1;
2337*4882a593Smuzhiyun ofs += mtd->eraseregions[i].numblocks << eraseshift;
2338*4882a593Smuzhiyun eraseshift++;
2339*4882a593Smuzhiyun } else {
2340*4882a593Smuzhiyun mtd->numeraseregions -= 1;
2341*4882a593Smuzhiyun mtd->eraseregions[i].numblocks +=
2342*4882a593Smuzhiyun this->boundary[die] + 1;
2343*4882a593Smuzhiyun ofs += (this->boundary[die] + 1) << (eraseshift - 1);
2344*4882a593Smuzhiyun }
2345*4882a593Smuzhiyun if (this->boundary[die] != maxbdry) {
2346*4882a593Smuzhiyun i++;
2347*4882a593Smuzhiyun mtd->eraseregions[i].offset = ofs;
2348*4882a593Smuzhiyun mtd->eraseregions[i].erasesize = 1 << eraseshift;
2349*4882a593Smuzhiyun mtd->eraseregions[i].numblocks = maxbdry ^
2350*4882a593Smuzhiyun this->boundary[die];
2351*4882a593Smuzhiyun ofs += mtd->eraseregions[i].numblocks << eraseshift;
2352*4882a593Smuzhiyun eraseshift--;
2353*4882a593Smuzhiyun } else
2354*4882a593Smuzhiyun mtd->numeraseregions -= 1;
2355*4882a593Smuzhiyun }
2356*4882a593Smuzhiyun
2357*4882a593Smuzhiyun /* Expose MLC erase size except when all blocks are SLC */
2358*4882a593Smuzhiyun mtd->erasesize = 1 << this->erase_shift;
2359*4882a593Smuzhiyun if (mtd->numeraseregions == 1)
2360*4882a593Smuzhiyun mtd->erasesize >>= 1;
2361*4882a593Smuzhiyun
2362*4882a593Smuzhiyun printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
2363*4882a593Smuzhiyun for (i = 0; i < mtd->numeraseregions; i++)
2364*4882a593Smuzhiyun printk(KERN_INFO "[offset: 0x%08llx, erasesize: 0x%05x,"
2365*4882a593Smuzhiyun " numblocks: %04u]\n", mtd->eraseregions[i].offset,
2366*4882a593Smuzhiyun mtd->eraseregions[i].erasesize,
2367*4882a593Smuzhiyun mtd->eraseregions[i].numblocks);
2368*4882a593Smuzhiyun
2369*4882a593Smuzhiyun for (die = 0, mtd->size = 0; die < this->dies; die++) {
2370*4882a593Smuzhiyun this->diesize[die] = (loff_t) (blksperdie << this->erase_shift);
2371*4882a593Smuzhiyun this->diesize[die] -= (loff_t) (this->boundary[die] + 1)
2372*4882a593Smuzhiyun << (this->erase_shift - 1);
2373*4882a593Smuzhiyun mtd->size += this->diesize[die];
2374*4882a593Smuzhiyun }
2375*4882a593Smuzhiyun }
2376*4882a593Smuzhiyun
2377*4882a593Smuzhiyun /**
2378*4882a593Smuzhiyun * flexonenand_check_blocks_erased - Check if blocks are erased
2379*4882a593Smuzhiyun * @param mtd_info - mtd info structure
2380*4882a593Smuzhiyun * @param start - first erase block to check
2381*4882a593Smuzhiyun * @param end - last erase block to check
2382*4882a593Smuzhiyun *
2383*4882a593Smuzhiyun * Converting an unerased block from MLC to SLC
2384*4882a593Smuzhiyun * causes byte values to change. Since both data and its ECC
2385*4882a593Smuzhiyun * have changed, reads on the block give uncorrectable error.
2386*4882a593Smuzhiyun * This might lead to the block being detected as bad.
2387*4882a593Smuzhiyun *
2388*4882a593Smuzhiyun * Avoid this by ensuring that the block to be converted is
2389*4882a593Smuzhiyun * erased.
2390*4882a593Smuzhiyun */
flexonenand_check_blocks_erased(struct mtd_info * mtd,int start,int end)2391*4882a593Smuzhiyun static int flexonenand_check_blocks_erased(struct mtd_info *mtd,
2392*4882a593Smuzhiyun int start, int end)
2393*4882a593Smuzhiyun {
2394*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2395*4882a593Smuzhiyun int i, ret;
2396*4882a593Smuzhiyun int block;
2397*4882a593Smuzhiyun struct mtd_oob_ops ops = {
2398*4882a593Smuzhiyun .mode = MTD_OPS_PLACE_OOB,
2399*4882a593Smuzhiyun .ooboffs = 0,
2400*4882a593Smuzhiyun .ooblen = mtd->oobsize,
2401*4882a593Smuzhiyun .datbuf = NULL,
2402*4882a593Smuzhiyun .oobbuf = this->oob_buf,
2403*4882a593Smuzhiyun };
2404*4882a593Smuzhiyun loff_t addr;
2405*4882a593Smuzhiyun
2406*4882a593Smuzhiyun printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
2407*4882a593Smuzhiyun
2408*4882a593Smuzhiyun for (block = start; block <= end; block++) {
2409*4882a593Smuzhiyun addr = flexonenand_addr(this, block);
2410*4882a593Smuzhiyun if (onenand_block_isbad_nolock(mtd, addr, 0))
2411*4882a593Smuzhiyun continue;
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun /*
2414*4882a593Smuzhiyun * Since main area write results in ECC write to spare,
2415*4882a593Smuzhiyun * it is sufficient to check only ECC bytes for change.
2416*4882a593Smuzhiyun */
2417*4882a593Smuzhiyun ret = onenand_read_oob_nolock(mtd, addr, &ops);
2418*4882a593Smuzhiyun if (ret)
2419*4882a593Smuzhiyun return ret;
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun for (i = 0; i < mtd->oobsize; i++)
2422*4882a593Smuzhiyun if (this->oob_buf[i] != 0xff)
2423*4882a593Smuzhiyun break;
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun if (i != mtd->oobsize) {
2426*4882a593Smuzhiyun printk(KERN_WARNING "Block %d not erased.\n", block);
2427*4882a593Smuzhiyun return 1;
2428*4882a593Smuzhiyun }
2429*4882a593Smuzhiyun }
2430*4882a593Smuzhiyun
2431*4882a593Smuzhiyun return 0;
2432*4882a593Smuzhiyun }
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun /**
2435*4882a593Smuzhiyun * flexonenand_set_boundary - Writes the SLC boundary
2436*4882a593Smuzhiyun * @param mtd - mtd info structure
2437*4882a593Smuzhiyun */
flexonenand_set_boundary(struct mtd_info * mtd,int die,int boundary,int lock)2438*4882a593Smuzhiyun int flexonenand_set_boundary(struct mtd_info *mtd, int die,
2439*4882a593Smuzhiyun int boundary, int lock)
2440*4882a593Smuzhiyun {
2441*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2442*4882a593Smuzhiyun int ret, density, blksperdie, old, new, thisboundary;
2443*4882a593Smuzhiyun loff_t addr;
2444*4882a593Smuzhiyun
2445*4882a593Smuzhiyun if (die >= this->dies)
2446*4882a593Smuzhiyun return -EINVAL;
2447*4882a593Smuzhiyun
2448*4882a593Smuzhiyun if (boundary == this->boundary[die])
2449*4882a593Smuzhiyun return 0;
2450*4882a593Smuzhiyun
2451*4882a593Smuzhiyun density = onenand_get_density(this->device_id);
2452*4882a593Smuzhiyun blksperdie = ((16 << density) << 20) >> this->erase_shift;
2453*4882a593Smuzhiyun blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
2454*4882a593Smuzhiyun
2455*4882a593Smuzhiyun if (boundary >= blksperdie) {
2456*4882a593Smuzhiyun printk("flexonenand_set_boundary:"
2457*4882a593Smuzhiyun "Invalid boundary value. "
2458*4882a593Smuzhiyun "Boundary not changed.\n");
2459*4882a593Smuzhiyun return -EINVAL;
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun /* Check if converting blocks are erased */
2463*4882a593Smuzhiyun old = this->boundary[die] + (die * this->density_mask);
2464*4882a593Smuzhiyun new = boundary + (die * this->density_mask);
2465*4882a593Smuzhiyun ret = flexonenand_check_blocks_erased(mtd, min(old, new)
2466*4882a593Smuzhiyun + 1, max(old, new));
2467*4882a593Smuzhiyun if (ret) {
2468*4882a593Smuzhiyun printk(KERN_ERR "flexonenand_set_boundary: Please erase blocks before boundary change\n");
2469*4882a593Smuzhiyun return ret;
2470*4882a593Smuzhiyun }
2471*4882a593Smuzhiyun
2472*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
2473*4882a593Smuzhiyun this->wait(mtd, FL_SYNCING);
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun /* Check is boundary is locked */
2476*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
2477*4882a593Smuzhiyun ret = this->wait(mtd, FL_READING);
2478*4882a593Smuzhiyun
2479*4882a593Smuzhiyun thisboundary = this->read_word(this->base + ONENAND_DATARAM);
2480*4882a593Smuzhiyun if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
2481*4882a593Smuzhiyun printk(KERN_ERR "flexonenand_set_boundary: boundary locked\n");
2482*4882a593Smuzhiyun goto out;
2483*4882a593Smuzhiyun }
2484*4882a593Smuzhiyun
2485*4882a593Smuzhiyun printk(KERN_INFO "flexonenand_set_boundary: Changing die %d boundary: %d%s\n",
2486*4882a593Smuzhiyun die, boundary, lock ? "(Locked)" : "(Unlocked)");
2487*4882a593Smuzhiyun
2488*4882a593Smuzhiyun boundary &= FLEXONENAND_PI_MASK;
2489*4882a593Smuzhiyun boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
2490*4882a593Smuzhiyun
2491*4882a593Smuzhiyun addr = die ? this->diesize[0] : 0;
2492*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
2493*4882a593Smuzhiyun ret = this->wait(mtd, FL_ERASING);
2494*4882a593Smuzhiyun if (ret) {
2495*4882a593Smuzhiyun printk("flexonenand_set_boundary:"
2496*4882a593Smuzhiyun "Failed PI erase for Die %d\n", die);
2497*4882a593Smuzhiyun goto out;
2498*4882a593Smuzhiyun }
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun this->write_word(boundary, this->base + ONENAND_DATARAM);
2501*4882a593Smuzhiyun this->command(mtd, ONENAND_CMD_PROG, addr, 0);
2502*4882a593Smuzhiyun ret = this->wait(mtd, FL_WRITING);
2503*4882a593Smuzhiyun if (ret) {
2504*4882a593Smuzhiyun printk("flexonenand_set_boundary:"
2505*4882a593Smuzhiyun "Failed PI write for Die %d\n", die);
2506*4882a593Smuzhiyun goto out;
2507*4882a593Smuzhiyun }
2508*4882a593Smuzhiyun
2509*4882a593Smuzhiyun this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
2510*4882a593Smuzhiyun ret = this->wait(mtd, FL_WRITING);
2511*4882a593Smuzhiyun out:
2512*4882a593Smuzhiyun this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
2513*4882a593Smuzhiyun this->wait(mtd, FL_RESETING);
2514*4882a593Smuzhiyun if (!ret)
2515*4882a593Smuzhiyun /* Recalculate device size on boundary change*/
2516*4882a593Smuzhiyun flexonenand_get_size(mtd);
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun return ret;
2519*4882a593Smuzhiyun }
2520*4882a593Smuzhiyun
2521*4882a593Smuzhiyun /**
2522*4882a593Smuzhiyun * onenand_chip_probe - [OneNAND Interface] Probe the OneNAND chip
2523*4882a593Smuzhiyun * @param mtd MTD device structure
2524*4882a593Smuzhiyun *
2525*4882a593Smuzhiyun * OneNAND detection method:
2526*4882a593Smuzhiyun * Compare the the values from command with ones from register
2527*4882a593Smuzhiyun */
onenand_chip_probe(struct mtd_info * mtd)2528*4882a593Smuzhiyun static int onenand_chip_probe(struct mtd_info *mtd)
2529*4882a593Smuzhiyun {
2530*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2531*4882a593Smuzhiyun int bram_maf_id, bram_dev_id, maf_id, dev_id;
2532*4882a593Smuzhiyun int syscfg;
2533*4882a593Smuzhiyun
2534*4882a593Smuzhiyun /* Save system configuration 1 */
2535*4882a593Smuzhiyun syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
2536*4882a593Smuzhiyun
2537*4882a593Smuzhiyun /* Clear Sync. Burst Read mode to read BootRAM */
2538*4882a593Smuzhiyun this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ),
2539*4882a593Smuzhiyun this->base + ONENAND_REG_SYS_CFG1);
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun /* Send the command for reading device ID from BootRAM */
2542*4882a593Smuzhiyun this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun /* Read manufacturer and device IDs from BootRAM */
2545*4882a593Smuzhiyun bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
2546*4882a593Smuzhiyun bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
2547*4882a593Smuzhiyun
2548*4882a593Smuzhiyun /* Reset OneNAND to read default register values */
2549*4882a593Smuzhiyun this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
2550*4882a593Smuzhiyun
2551*4882a593Smuzhiyun /* Wait reset */
2552*4882a593Smuzhiyun if (this->wait(mtd, FL_RESETING))
2553*4882a593Smuzhiyun return -ENXIO;
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun /* Restore system configuration 1 */
2556*4882a593Smuzhiyun this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
2557*4882a593Smuzhiyun
2558*4882a593Smuzhiyun /* Check manufacturer ID */
2559*4882a593Smuzhiyun if (onenand_check_maf(bram_maf_id))
2560*4882a593Smuzhiyun return -ENXIO;
2561*4882a593Smuzhiyun
2562*4882a593Smuzhiyun /* Read manufacturer and device IDs from Register */
2563*4882a593Smuzhiyun maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
2564*4882a593Smuzhiyun dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
2565*4882a593Smuzhiyun
2566*4882a593Smuzhiyun /* Check OneNAND device */
2567*4882a593Smuzhiyun if (maf_id != bram_maf_id || dev_id != bram_dev_id)
2568*4882a593Smuzhiyun return -ENXIO;
2569*4882a593Smuzhiyun
2570*4882a593Smuzhiyun return 0;
2571*4882a593Smuzhiyun }
2572*4882a593Smuzhiyun
2573*4882a593Smuzhiyun /**
2574*4882a593Smuzhiyun * onenand_probe - [OneNAND Interface] Probe the OneNAND device
2575*4882a593Smuzhiyun * @param mtd MTD device structure
2576*4882a593Smuzhiyun *
2577*4882a593Smuzhiyun * OneNAND detection method:
2578*4882a593Smuzhiyun * Compare the the values from command with ones from register
2579*4882a593Smuzhiyun */
onenand_probe(struct mtd_info * mtd)2580*4882a593Smuzhiyun int onenand_probe(struct mtd_info *mtd)
2581*4882a593Smuzhiyun {
2582*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2583*4882a593Smuzhiyun int dev_id, ver_id;
2584*4882a593Smuzhiyun int density;
2585*4882a593Smuzhiyun int ret;
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun ret = this->chip_probe(mtd);
2588*4882a593Smuzhiyun if (ret)
2589*4882a593Smuzhiyun return ret;
2590*4882a593Smuzhiyun
2591*4882a593Smuzhiyun /* Read device IDs from Register */
2592*4882a593Smuzhiyun dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
2593*4882a593Smuzhiyun ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
2594*4882a593Smuzhiyun this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
2595*4882a593Smuzhiyun
2596*4882a593Smuzhiyun /* Flash device information */
2597*4882a593Smuzhiyun mtd->name = onenand_print_device_info(dev_id, ver_id);
2598*4882a593Smuzhiyun this->device_id = dev_id;
2599*4882a593Smuzhiyun this->version_id = ver_id;
2600*4882a593Smuzhiyun
2601*4882a593Smuzhiyun /* Check OneNAND features */
2602*4882a593Smuzhiyun onenand_check_features(mtd);
2603*4882a593Smuzhiyun
2604*4882a593Smuzhiyun density = onenand_get_density(dev_id);
2605*4882a593Smuzhiyun if (FLEXONENAND(this)) {
2606*4882a593Smuzhiyun this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
2607*4882a593Smuzhiyun /* Maximum possible erase regions */
2608*4882a593Smuzhiyun mtd->numeraseregions = this->dies << 1;
2609*4882a593Smuzhiyun mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info)
2610*4882a593Smuzhiyun * (this->dies << 1));
2611*4882a593Smuzhiyun if (!mtd->eraseregions)
2612*4882a593Smuzhiyun return -ENOMEM;
2613*4882a593Smuzhiyun }
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun /*
2616*4882a593Smuzhiyun * For Flex-OneNAND, chipsize represents maximum possible device size.
2617*4882a593Smuzhiyun * mtd->size represents the actual device size.
2618*4882a593Smuzhiyun */
2619*4882a593Smuzhiyun this->chipsize = (16 << density) << 20;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun /* OneNAND page size & block size */
2622*4882a593Smuzhiyun /* The data buffer size is equal to page size */
2623*4882a593Smuzhiyun mtd->writesize =
2624*4882a593Smuzhiyun this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
2625*4882a593Smuzhiyun /* We use the full BufferRAM */
2626*4882a593Smuzhiyun if (ONENAND_IS_4KB_PAGE(this))
2627*4882a593Smuzhiyun mtd->writesize <<= 1;
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun mtd->oobsize = mtd->writesize >> 5;
2630*4882a593Smuzhiyun /* Pagers per block is always 64 in OneNAND */
2631*4882a593Smuzhiyun mtd->erasesize = mtd->writesize << 6;
2632*4882a593Smuzhiyun /*
2633*4882a593Smuzhiyun * Flex-OneNAND SLC area has 64 pages per block.
2634*4882a593Smuzhiyun * Flex-OneNAND MLC area has 128 pages per block.
2635*4882a593Smuzhiyun * Expose MLC erase size to find erase_shift and page_mask.
2636*4882a593Smuzhiyun */
2637*4882a593Smuzhiyun if (FLEXONENAND(this))
2638*4882a593Smuzhiyun mtd->erasesize <<= 1;
2639*4882a593Smuzhiyun
2640*4882a593Smuzhiyun this->erase_shift = ffs(mtd->erasesize) - 1;
2641*4882a593Smuzhiyun this->page_shift = ffs(mtd->writesize) - 1;
2642*4882a593Smuzhiyun this->ppb_shift = (this->erase_shift - this->page_shift);
2643*4882a593Smuzhiyun this->page_mask = (mtd->erasesize / mtd->writesize) - 1;
2644*4882a593Smuzhiyun /* Set density mask. it is used for DDP */
2645*4882a593Smuzhiyun if (ONENAND_IS_DDP(this))
2646*4882a593Smuzhiyun this->density_mask = this->chipsize >> (this->erase_shift + 1);
2647*4882a593Smuzhiyun /* It's real page size */
2648*4882a593Smuzhiyun this->writesize = mtd->writesize;
2649*4882a593Smuzhiyun
2650*4882a593Smuzhiyun /* REVIST: Multichip handling */
2651*4882a593Smuzhiyun
2652*4882a593Smuzhiyun if (FLEXONENAND(this))
2653*4882a593Smuzhiyun flexonenand_get_size(mtd);
2654*4882a593Smuzhiyun else
2655*4882a593Smuzhiyun mtd->size = this->chipsize;
2656*4882a593Smuzhiyun
2657*4882a593Smuzhiyun mtd->flags = MTD_CAP_NANDFLASH;
2658*4882a593Smuzhiyun mtd->_erase = onenand_erase;
2659*4882a593Smuzhiyun mtd->_read_oob = onenand_read_oob;
2660*4882a593Smuzhiyun mtd->_write_oob = onenand_write_oob;
2661*4882a593Smuzhiyun mtd->_sync = onenand_sync;
2662*4882a593Smuzhiyun mtd->_block_isbad = onenand_block_isbad;
2663*4882a593Smuzhiyun mtd->_block_markbad = onenand_block_markbad;
2664*4882a593Smuzhiyun mtd->writebufsize = mtd->writesize;
2665*4882a593Smuzhiyun
2666*4882a593Smuzhiyun return 0;
2667*4882a593Smuzhiyun }
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun /**
2670*4882a593Smuzhiyun * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
2671*4882a593Smuzhiyun * @param mtd MTD device structure
2672*4882a593Smuzhiyun * @param maxchips Number of chips to scan for
2673*4882a593Smuzhiyun *
2674*4882a593Smuzhiyun * This fills out all the not initialized function pointers
2675*4882a593Smuzhiyun * with the defaults.
2676*4882a593Smuzhiyun * The flash ID is read and the mtd/chip structures are
2677*4882a593Smuzhiyun * filled with the appropriate values.
2678*4882a593Smuzhiyun */
onenand_scan(struct mtd_info * mtd,int maxchips)2679*4882a593Smuzhiyun int onenand_scan(struct mtd_info *mtd, int maxchips)
2680*4882a593Smuzhiyun {
2681*4882a593Smuzhiyun int i;
2682*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
2683*4882a593Smuzhiyun
2684*4882a593Smuzhiyun if (!this->read_word)
2685*4882a593Smuzhiyun this->read_word = onenand_readw;
2686*4882a593Smuzhiyun if (!this->write_word)
2687*4882a593Smuzhiyun this->write_word = onenand_writew;
2688*4882a593Smuzhiyun
2689*4882a593Smuzhiyun if (!this->command)
2690*4882a593Smuzhiyun this->command = onenand_command;
2691*4882a593Smuzhiyun if (!this->wait)
2692*4882a593Smuzhiyun this->wait = onenand_wait;
2693*4882a593Smuzhiyun if (!this->bbt_wait)
2694*4882a593Smuzhiyun this->bbt_wait = onenand_bbt_wait;
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun if (!this->read_bufferram)
2697*4882a593Smuzhiyun this->read_bufferram = onenand_read_bufferram;
2698*4882a593Smuzhiyun if (!this->write_bufferram)
2699*4882a593Smuzhiyun this->write_bufferram = onenand_write_bufferram;
2700*4882a593Smuzhiyun
2701*4882a593Smuzhiyun if (!this->chip_probe)
2702*4882a593Smuzhiyun this->chip_probe = onenand_chip_probe;
2703*4882a593Smuzhiyun
2704*4882a593Smuzhiyun if (!this->block_markbad)
2705*4882a593Smuzhiyun this->block_markbad = onenand_default_block_markbad;
2706*4882a593Smuzhiyun if (!this->scan_bbt)
2707*4882a593Smuzhiyun this->scan_bbt = onenand_default_bbt;
2708*4882a593Smuzhiyun
2709*4882a593Smuzhiyun if (onenand_probe(mtd))
2710*4882a593Smuzhiyun return -ENXIO;
2711*4882a593Smuzhiyun
2712*4882a593Smuzhiyun /* Set Sync. Burst Read after probing */
2713*4882a593Smuzhiyun if (this->mmcontrol) {
2714*4882a593Smuzhiyun printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
2715*4882a593Smuzhiyun this->read_bufferram = onenand_sync_read_bufferram;
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun /* Allocate buffers, if necessary */
2719*4882a593Smuzhiyun if (!this->page_buf) {
2720*4882a593Smuzhiyun this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL);
2721*4882a593Smuzhiyun if (!this->page_buf) {
2722*4882a593Smuzhiyun printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n");
2723*4882a593Smuzhiyun return -ENOMEM;
2724*4882a593Smuzhiyun }
2725*4882a593Smuzhiyun this->options |= ONENAND_PAGEBUF_ALLOC;
2726*4882a593Smuzhiyun }
2727*4882a593Smuzhiyun if (!this->oob_buf) {
2728*4882a593Smuzhiyun this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
2729*4882a593Smuzhiyun if (!this->oob_buf) {
2730*4882a593Smuzhiyun printk(KERN_ERR "onenand_scan: Can't allocate oob_buf\n");
2731*4882a593Smuzhiyun if (this->options & ONENAND_PAGEBUF_ALLOC) {
2732*4882a593Smuzhiyun this->options &= ~ONENAND_PAGEBUF_ALLOC;
2733*4882a593Smuzhiyun kfree(this->page_buf);
2734*4882a593Smuzhiyun }
2735*4882a593Smuzhiyun return -ENOMEM;
2736*4882a593Smuzhiyun }
2737*4882a593Smuzhiyun this->options |= ONENAND_OOBBUF_ALLOC;
2738*4882a593Smuzhiyun }
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun this->state = FL_READY;
2741*4882a593Smuzhiyun
2742*4882a593Smuzhiyun /*
2743*4882a593Smuzhiyun * Allow subpage writes up to oobsize.
2744*4882a593Smuzhiyun */
2745*4882a593Smuzhiyun switch (mtd->oobsize) {
2746*4882a593Smuzhiyun case 128:
2747*4882a593Smuzhiyun this->ecclayout = &onenand_oob_128;
2748*4882a593Smuzhiyun mtd->subpage_sft = 0;
2749*4882a593Smuzhiyun break;
2750*4882a593Smuzhiyun
2751*4882a593Smuzhiyun case 64:
2752*4882a593Smuzhiyun this->ecclayout = &onenand_oob_64;
2753*4882a593Smuzhiyun mtd->subpage_sft = 2;
2754*4882a593Smuzhiyun break;
2755*4882a593Smuzhiyun
2756*4882a593Smuzhiyun case 32:
2757*4882a593Smuzhiyun this->ecclayout = &onenand_oob_32;
2758*4882a593Smuzhiyun mtd->subpage_sft = 1;
2759*4882a593Smuzhiyun break;
2760*4882a593Smuzhiyun
2761*4882a593Smuzhiyun default:
2762*4882a593Smuzhiyun printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
2763*4882a593Smuzhiyun mtd->oobsize);
2764*4882a593Smuzhiyun mtd->subpage_sft = 0;
2765*4882a593Smuzhiyun /* To prevent kernel oops */
2766*4882a593Smuzhiyun this->ecclayout = &onenand_oob_32;
2767*4882a593Smuzhiyun break;
2768*4882a593Smuzhiyun }
2769*4882a593Smuzhiyun
2770*4882a593Smuzhiyun this->subpagesize = mtd->writesize >> mtd->subpage_sft;
2771*4882a593Smuzhiyun
2772*4882a593Smuzhiyun /*
2773*4882a593Smuzhiyun * The number of bytes available for a client to place data into
2774*4882a593Smuzhiyun * the out of band area
2775*4882a593Smuzhiyun */
2776*4882a593Smuzhiyun this->ecclayout->oobavail = 0;
2777*4882a593Smuzhiyun
2778*4882a593Smuzhiyun for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE &&
2779*4882a593Smuzhiyun this->ecclayout->oobfree[i].length; i++)
2780*4882a593Smuzhiyun this->ecclayout->oobavail +=
2781*4882a593Smuzhiyun this->ecclayout->oobfree[i].length;
2782*4882a593Smuzhiyun mtd->oobavail = this->ecclayout->oobavail;
2783*4882a593Smuzhiyun
2784*4882a593Smuzhiyun mtd->ecclayout = this->ecclayout;
2785*4882a593Smuzhiyun
2786*4882a593Smuzhiyun /* Unlock whole block */
2787*4882a593Smuzhiyun onenand_unlock_all(mtd);
2788*4882a593Smuzhiyun
2789*4882a593Smuzhiyun return this->scan_bbt(mtd);
2790*4882a593Smuzhiyun }
2791*4882a593Smuzhiyun
2792*4882a593Smuzhiyun /**
2793*4882a593Smuzhiyun * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
2794*4882a593Smuzhiyun * @param mtd MTD device structure
2795*4882a593Smuzhiyun */
onenand_release(struct mtd_info * mtd)2796*4882a593Smuzhiyun void onenand_release(struct mtd_info *mtd)
2797*4882a593Smuzhiyun {
2798*4882a593Smuzhiyun }
2799