1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Dingqiang Lin <jon.lin@rock-chips.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __UBOOT__
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #endif
13*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SPINAND_MFR_XINCUN 0x8C
16*4882a593Smuzhiyun #define XINCUN_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
21*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
22*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
23*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
24*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
27*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
28*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
31*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
32*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
33*4882a593Smuzhiyun
xcsp2aapk_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)34*4882a593Smuzhiyun static int xcsp2aapk_ooblayout_ecc(struct mtd_info *mtd, int section,
35*4882a593Smuzhiyun struct mtd_oob_region *region)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun if (section)
38*4882a593Smuzhiyun return -ERANGE;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun region->offset = mtd->oobsize / 2;
41*4882a593Smuzhiyun region->length = mtd->oobsize / 2;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
xcsp2aapk_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)46*4882a593Smuzhiyun static int xcsp2aapk_ooblayout_free(struct mtd_info *mtd, int section,
47*4882a593Smuzhiyun struct mtd_oob_region *region)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun if (section)
50*4882a593Smuzhiyun return -ERANGE;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Reserve 2 bytes for the BBM. */
53*4882a593Smuzhiyun region->offset = 2;
54*4882a593Smuzhiyun region->length = mtd->oobsize / 2 - 2;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct mtd_ooblayout_ops xcsp2aapk_ooblayout = {
60*4882a593Smuzhiyun .ecc = xcsp2aapk_ooblayout_ecc,
61*4882a593Smuzhiyun .rfree = xcsp2aapk_ooblayout_free,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
xcsp2aapk_ecc_get_status(struct spinand_device * spinand,u8 status)64*4882a593Smuzhiyun static int xcsp2aapk_ecc_get_status(struct spinand_device *spinand,
65*4882a593Smuzhiyun u8 status)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
70*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
74*4882a593Smuzhiyun return -EBADMSG;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case STATUS_ECC_HAS_BITFLIPS:
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun case XINCUN_STATUS_ECC_HAS_BITFLIPS_T:
79*4882a593Smuzhiyun return nand->eccreq.strength;
80*4882a593Smuzhiyun default:
81*4882a593Smuzhiyun break;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return -EINVAL;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static const struct spinand_info xincun_spinand_table[] = {
88*4882a593Smuzhiyun SPINAND_INFO("XCSP2AAPK",
89*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xA1),
90*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
91*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
92*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
93*4882a593Smuzhiyun &write_cache_variants,
94*4882a593Smuzhiyun &update_cache_variants),
95*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
96*4882a593Smuzhiyun SPINAND_ECCINFO(&xcsp2aapk_ooblayout, xcsp2aapk_ecc_get_status)),
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct spinand_manufacturer_ops xincun_spinand_manuf_ops = {
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun const struct spinand_manufacturer xincun_spinand_manufacturer = {
103*4882a593Smuzhiyun .id = SPINAND_MFR_XINCUN,
104*4882a593Smuzhiyun .name = "XINCUN",
105*4882a593Smuzhiyun .chips = xincun_spinand_table,
106*4882a593Smuzhiyun .nchips = ARRAY_SIZE(xincun_spinand_table),
107*4882a593Smuzhiyun .ops = &xincun_spinand_manuf_ops,
108*4882a593Smuzhiyun };
109