1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Dingqiang Lin <jon.lin@rock-chips.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __UBOOT__
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #endif
13*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SPINAND_MFR_UNIM 0xA1
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
18*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
21*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
22*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
23*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
26*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
27*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
30*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
31*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
32*4882a593Smuzhiyun
tx25g01_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)33*4882a593Smuzhiyun static int tx25g01_ooblayout_ecc(struct mtd_info *mtd, int section,
34*4882a593Smuzhiyun struct mtd_oob_region *region)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun if (section > 3)
37*4882a593Smuzhiyun return -ERANGE;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun region->offset = (16 * section) + 8;
40*4882a593Smuzhiyun region->length = 8;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
tx25g01_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)45*4882a593Smuzhiyun static int tx25g01_ooblayout_free(struct mtd_info *mtd, int section,
46*4882a593Smuzhiyun struct mtd_oob_region *region)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun if (section > 3)
49*4882a593Smuzhiyun return -ERANGE;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun region->offset = (16 * section) + 2;
52*4882a593Smuzhiyun region->length = 6;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static const struct mtd_ooblayout_ops tx25g01_ooblayout = {
58*4882a593Smuzhiyun .ecc = tx25g01_ooblayout_ecc,
59*4882a593Smuzhiyun .rfree = tx25g01_ooblayout_free,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * ecc bits: 0xC0[4,6]
64*4882a593Smuzhiyun * [0b000], No bit errors were detected;
65*4882a593Smuzhiyun * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not
66*4882a593Smuzhiyun * reach Flipping Bits;
67*4882a593Smuzhiyun * [0b100], Bit error count equals the bit flip
68*4882a593Smuzhiyun * detection threshold
69*4882a593Smuzhiyun * others, Reserved.
70*4882a593Smuzhiyun */
tx25g01_ecc_get_status(struct spinand_device * spinand,u8 status)71*4882a593Smuzhiyun static int tx25g01_ecc_get_status(struct spinand_device *spinand,
72*4882a593Smuzhiyun u8 status)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
75*4882a593Smuzhiyun u8 eccsr = (status & GENMASK(6, 4)) >> 4;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (eccsr < 4)
78*4882a593Smuzhiyun return eccsr;
79*4882a593Smuzhiyun else if (eccsr == 4)
80*4882a593Smuzhiyun return nand->eccreq.strength;
81*4882a593Smuzhiyun else
82*4882a593Smuzhiyun return -EBADMSG;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct spinand_info unim_spinand_table[] = {
86*4882a593Smuzhiyun SPINAND_INFO("TX25G01",
87*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1),
88*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
89*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
90*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
91*4882a593Smuzhiyun &write_cache_variants,
92*4882a593Smuzhiyun &update_cache_variants),
93*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
94*4882a593Smuzhiyun SPINAND_ECCINFO(&tx25g01_ooblayout, tx25g01_ecc_get_status)),
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct spinand_manufacturer_ops unim_spinand_manuf_ops = {
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun const struct spinand_manufacturer unim_spinand_manufacturer = {
101*4882a593Smuzhiyun .id = SPINAND_MFR_UNIM,
102*4882a593Smuzhiyun .name = "UNIM",
103*4882a593Smuzhiyun .chips = unim_spinand_table,
104*4882a593Smuzhiyun .nchips = ARRAY_SIZE(unim_spinand_table),
105*4882a593Smuzhiyun .ops = &unim_spinand_manuf_ops,
106*4882a593Smuzhiyun };
107