1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Dingqiang Lin <jon.lin@rock-chips.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __UBOOT__
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #endif
13*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SPINAND_MFR_SKYHIGH 0x01
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SKYHIGH_STATUS_ECC_1_2_BITFLIPS (1 << 4)
18*4882a593Smuzhiyun #define SKYHIGH_STATUS_ECC_3_4_BITFLIPS (2 << 4)
19*4882a593Smuzhiyun #define SKYHIGH_STATUS_ECC_UNCOR_ERROR (3 << 4)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
22*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
23*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
24*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
25*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
26*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
27*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
30*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
31*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
34*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
35*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
36*4882a593Smuzhiyun
s35ml04g3_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)37*4882a593Smuzhiyun static int s35ml04g3_ooblayout_ecc(struct mtd_info *mtd, int section,
38*4882a593Smuzhiyun struct mtd_oob_region *region)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return -ERANGE;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
s35ml04g3_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)43*4882a593Smuzhiyun static int s35ml04g3_ooblayout_free(struct mtd_info *mtd, int section,
44*4882a593Smuzhiyun struct mtd_oob_region *region)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun if (section)
47*4882a593Smuzhiyun return -ERANGE;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun region->offset = 2;
50*4882a593Smuzhiyun region->length = mtd->oobsize - 2;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct mtd_ooblayout_ops s35ml04g3_ooblayout = {
56*4882a593Smuzhiyun .ecc = s35ml04g3_ooblayout_ecc,
57*4882a593Smuzhiyun .rfree = s35ml04g3_ooblayout_free,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun
s35ml0xg3_ecc_get_status(struct spinand_device * spinand,u8 status)61*4882a593Smuzhiyun static int s35ml0xg3_ecc_get_status(struct spinand_device *spinand,
62*4882a593Smuzhiyun u8 status)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
67*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun case SKYHIGH_STATUS_ECC_UNCOR_ERROR:
71*4882a593Smuzhiyun return -EBADMSG;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun case SKYHIGH_STATUS_ECC_1_2_BITFLIPS:
74*4882a593Smuzhiyun return 2;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun default:
77*4882a593Smuzhiyun return nand->eccreq.strength;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return -EINVAL;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct spinand_info skyhigh_spinand_table[] = {
84*4882a593Smuzhiyun SPINAND_INFO("S35ML01G3",
85*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
86*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 2, 1, 1),
87*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
88*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
89*4882a593Smuzhiyun &write_cache_variants,
90*4882a593Smuzhiyun &update_cache_variants),
91*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
92*4882a593Smuzhiyun SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
93*4882a593Smuzhiyun SPINAND_INFO("S35ML02G3",
94*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
95*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
96*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
97*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
98*4882a593Smuzhiyun &write_cache_variants,
99*4882a593Smuzhiyun &update_cache_variants),
100*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
101*4882a593Smuzhiyun SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
102*4882a593Smuzhiyun SPINAND_INFO("S35ML04G3",
103*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
104*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
105*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
106*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
107*4882a593Smuzhiyun &write_cache_variants,
108*4882a593Smuzhiyun &update_cache_variants),
109*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
110*4882a593Smuzhiyun SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static const struct spinand_manufacturer_ops skyhigh_spinand_manuf_ops = {
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun const struct spinand_manufacturer skyhigh_spinand_manufacturer = {
117*4882a593Smuzhiyun .id = SPINAND_MFR_SKYHIGH,
118*4882a593Smuzhiyun .name = "skyhigh",
119*4882a593Smuzhiyun .chips = skyhigh_spinand_table,
120*4882a593Smuzhiyun .nchips = ARRAY_SIZE(skyhigh_spinand_table),
121*4882a593Smuzhiyun .ops = &skyhigh_spinand_manuf_ops,
122*4882a593Smuzhiyun };
123