1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016-2017 Micron Technology, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Peter Pan <peterpandong@micron.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __UBOOT__
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #endif
13*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SPINAND_MFR_MICRON 0x2c
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MICRON_STATUS_ECC_MASK GENMASK(7, 4)
18*4882a593Smuzhiyun #define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4)
19*4882a593Smuzhiyun #define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
20*4882a593Smuzhiyun #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
21*4882a593Smuzhiyun #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
24*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
25*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
26*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
27*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
28*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
29*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
32*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
33*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
36*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
37*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
38*4882a593Smuzhiyun
mt29f2g01abagd_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)39*4882a593Smuzhiyun static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
40*4882a593Smuzhiyun struct mtd_oob_region *region)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun if (section)
43*4882a593Smuzhiyun return -ERANGE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun region->offset = 64;
46*4882a593Smuzhiyun region->length = 64;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
mt29f2g01abagd_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)51*4882a593Smuzhiyun static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
52*4882a593Smuzhiyun struct mtd_oob_region *region)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun if (section)
55*4882a593Smuzhiyun return -ERANGE;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Reserve 2 bytes for the BBM. */
58*4882a593Smuzhiyun region->offset = 2;
59*4882a593Smuzhiyun region->length = 62;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
65*4882a593Smuzhiyun .ecc = mt29f2g01abagd_ooblayout_ecc,
66*4882a593Smuzhiyun .rfree = mt29f2g01abagd_ooblayout_free,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
mt29f2g01abagd_ecc_get_status(struct spinand_device * spinand,u8 status)69*4882a593Smuzhiyun static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
70*4882a593Smuzhiyun u8 status)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun switch (status & MICRON_STATUS_ECC_MASK) {
73*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
77*4882a593Smuzhiyun return -EBADMSG;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun case MICRON_STATUS_ECC_1TO3_BITFLIPS:
80*4882a593Smuzhiyun return 3;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun case MICRON_STATUS_ECC_4TO6_BITFLIPS:
83*4882a593Smuzhiyun return 6;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun case MICRON_STATUS_ECC_7TO8_BITFLIPS:
86*4882a593Smuzhiyun return 8;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun default:
89*4882a593Smuzhiyun break;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return -EINVAL;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const struct spinand_info micron_spinand_table[] = {
96*4882a593Smuzhiyun SPINAND_INFO("MT29F2G01ABAGD",
97*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
98*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
99*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
100*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
101*4882a593Smuzhiyun &write_cache_variants,
102*4882a593Smuzhiyun &update_cache_variants),
103*4882a593Smuzhiyun 0,
104*4882a593Smuzhiyun SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
105*4882a593Smuzhiyun mt29f2g01abagd_ecc_get_status)),
106*4882a593Smuzhiyun SPINAND_INFO("MT29F1G01ABAGD",
107*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
108*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
109*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
110*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
111*4882a593Smuzhiyun &write_cache_variants,
112*4882a593Smuzhiyun &update_cache_variants),
113*4882a593Smuzhiyun 0,
114*4882a593Smuzhiyun SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
115*4882a593Smuzhiyun mt29f2g01abagd_ecc_get_status)),
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun const struct spinand_manufacturer micron_spinand_manufacturer = {
122*4882a593Smuzhiyun .id = SPINAND_MFR_MICRON,
123*4882a593Smuzhiyun .name = "Micron",
124*4882a593Smuzhiyun .chips = micron_spinand_table,
125*4882a593Smuzhiyun .nchips = ARRAY_SIZE(micron_spinand_table),
126*4882a593Smuzhiyun .ops = µn_spinand_manuf_ops,
127*4882a593Smuzhiyun };
128