1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __UBOOT__
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #endif
10*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SPINAND_MFR_ETRON 0xD5
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
15*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
16*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
17*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
18*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
23*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
24*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
27*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
28*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
29*4882a593Smuzhiyun
em73c044vcf_oh_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)30*4882a593Smuzhiyun static int em73c044vcf_oh_ooblayout_ecc(struct mtd_info *mtd, int section,
31*4882a593Smuzhiyun struct mtd_oob_region *region)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun if (section > 3)
34*4882a593Smuzhiyun return -ERANGE;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun region->offset = (16 * section) + 8;
37*4882a593Smuzhiyun region->length = 8;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
em73c044vcf_oh_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)42*4882a593Smuzhiyun static int em73c044vcf_oh_ooblayout_free(struct mtd_info *mtd, int section,
43*4882a593Smuzhiyun struct mtd_oob_region *region)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun if (section > 3)
46*4882a593Smuzhiyun return -ERANGE;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun region->offset = (16 * section) + 2;
49*4882a593Smuzhiyun region->length = 6;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct mtd_ooblayout_ops em73c044vcf_oh_ooblayout = {
55*4882a593Smuzhiyun .ecc = em73c044vcf_oh_ooblayout_ecc,
56*4882a593Smuzhiyun .rfree = em73c044vcf_oh_ooblayout_free,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
em73c044vcf_oh_ecc_get_status(struct spinand_device * spinand,u8 status)59*4882a593Smuzhiyun static int em73c044vcf_oh_ecc_get_status(struct spinand_device *spinand,
60*4882a593Smuzhiyun u8 status)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
65*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
69*4882a593Smuzhiyun return -EBADMSG;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun case STATUS_ECC_HAS_BITFLIPS:
72*4882a593Smuzhiyun return 1;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun default:
75*4882a593Smuzhiyun return nand->eccreq.strength;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return -EINVAL;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct spinand_info etron_spinand_table[] = {
82*4882a593Smuzhiyun SPINAND_INFO("EM73C044VCF-0H",
83*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x36),
84*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
85*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
86*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
87*4882a593Smuzhiyun &write_cache_variants,
88*4882a593Smuzhiyun &update_cache_variants),
89*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
90*4882a593Smuzhiyun SPINAND_ECCINFO(&em73c044vcf_oh_ooblayout,
91*4882a593Smuzhiyun em73c044vcf_oh_ecc_get_status)),
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun const struct spinand_manufacturer etron_spinand_manufacturer = {
98*4882a593Smuzhiyun .id = SPINAND_MFR_ETRON,
99*4882a593Smuzhiyun .name = "Etron",
100*4882a593Smuzhiyun .chips = etron_spinand_table,
101*4882a593Smuzhiyun .nchips = ARRAY_SIZE(etron_spinand_table),
102*4882a593Smuzhiyun .ops = &etron_spinand_manuf_ops,
103*4882a593Smuzhiyun };
104