1*4882a593Smuzhiyun #ifndef __ASM_ARCH_PXA3XX_NAND_H 2*4882a593Smuzhiyun #define __ASM_ARCH_PXA3XX_NAND_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <linux/mtd/mtd.h> 5*4882a593Smuzhiyun #include <linux/mtd/partitions.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct pxa3xx_nand_timing { 8*4882a593Smuzhiyun unsigned int tCH; /* Enable signal hold time */ 9*4882a593Smuzhiyun unsigned int tCS; /* Enable signal setup time */ 10*4882a593Smuzhiyun unsigned int tWH; /* ND_nWE high duration */ 11*4882a593Smuzhiyun unsigned int tWP; /* ND_nWE pulse time */ 12*4882a593Smuzhiyun unsigned int tRH; /* ND_nRE high duration */ 13*4882a593Smuzhiyun unsigned int tRP; /* ND_nRE pulse width */ 14*4882a593Smuzhiyun unsigned int tR; /* ND_nWE high to ND_nRE low for read */ 15*4882a593Smuzhiyun unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ 16*4882a593Smuzhiyun unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct pxa3xx_nand_flash { 20*4882a593Smuzhiyun uint32_t chip_id; 21*4882a593Smuzhiyun unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */ 22*4882a593Smuzhiyun unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */ 23*4882a593Smuzhiyun struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Current pxa3xx_nand controller has two chip select which 28*4882a593Smuzhiyun * both be workable. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Notice should be taken that: 31*4882a593Smuzhiyun * When you want to use this feature, you should not enable the 32*4882a593Smuzhiyun * keep configuration feature, for two chip select could be 33*4882a593Smuzhiyun * attached with different nand chip. The different page size 34*4882a593Smuzhiyun * and timing requirement make the keep configuration impossible. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* The max num of chip select current support */ 38*4882a593Smuzhiyun #define NUM_CHIP_SELECT (2) 39*4882a593Smuzhiyun struct pxa3xx_nand_platform_data { 40*4882a593Smuzhiyun /* the data flash bus is shared between the Static Memory 41*4882a593Smuzhiyun * Controller and the Data Flash Controller, the arbiter 42*4882a593Smuzhiyun * controls the ownership of the bus 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun int enable_arbiter; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* allow platform code to keep OBM/bootloader defined NFC config */ 47*4882a593Smuzhiyun int keep_config; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* indicate how many chip selects will be used */ 50*4882a593Smuzhiyun int num_cs; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* use an flash-based bad block table */ 53*4882a593Smuzhiyun bool flash_bbt; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* requested ECC strength and ECC step size */ 56*4882a593Smuzhiyun int ecc_strength, ecc_step_size; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun const struct mtd_partition *parts[NUM_CHIP_SELECT]; 59*4882a593Smuzhiyun unsigned int nr_parts[NUM_CHIP_SELECT]; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun const struct pxa3xx_nand_flash *flash; 62*4882a593Smuzhiyun size_t num_flash; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun #endif /* __ASM_ARCH_PXA3XX_NAND_H */ 65