1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Genericish driver for memory mapped NAND devices 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2006-2009 Analog Devices Inc. 5*4882a593Smuzhiyun * Licensed under the GPL-2 or later. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Your board must implement the following macros: 9*4882a593Smuzhiyun * NAND_PLAT_WRITE_CMD(chip, cmd) 10*4882a593Smuzhiyun * NAND_PLAT_WRITE_ADR(chip, cmd) 11*4882a593Smuzhiyun * NAND_PLAT_INIT() 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * It may also implement the following: 14*4882a593Smuzhiyun * NAND_PLAT_DEV_READY(chip) 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <common.h> 18*4882a593Smuzhiyun #include <asm/io.h> 19*4882a593Smuzhiyun #ifdef NAND_PLAT_GPIO_DEV_READY 20*4882a593Smuzhiyun # include <asm/gpio.h> 21*4882a593Smuzhiyun # define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <nand.h> 25*4882a593Smuzhiyun plat_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)26*4882a593Smuzhiyunstatic void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun struct nand_chip *this = mtd_to_nand(mtd); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun if (cmd == NAND_CMD_NONE) 31*4882a593Smuzhiyun return; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun if (ctrl & NAND_CLE) 34*4882a593Smuzhiyun NAND_PLAT_WRITE_CMD(this, cmd); 35*4882a593Smuzhiyun else 36*4882a593Smuzhiyun NAND_PLAT_WRITE_ADR(this, cmd); 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #ifdef NAND_PLAT_DEV_READY plat_dev_ready(struct mtd_info * mtd)40*4882a593Smuzhiyunstatic int plat_dev_ready(struct mtd_info *mtd) 41*4882a593Smuzhiyun { 42*4882a593Smuzhiyun return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd)); 43*4882a593Smuzhiyun } 44*4882a593Smuzhiyun #else 45*4882a593Smuzhiyun # define plat_dev_ready NULL 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun board_nand_init(struct nand_chip * nand)48*4882a593Smuzhiyunint board_nand_init(struct nand_chip *nand) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun #ifdef NAND_PLAT_GPIO_DEV_READY 51*4882a593Smuzhiyun gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); 52*4882a593Smuzhiyun gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef NAND_PLAT_INIT 56*4882a593Smuzhiyun NAND_PLAT_INIT(); 57*4882a593Smuzhiyun #endif 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun nand->cmd_ctrl = plat_cmd_ctrl; 60*4882a593Smuzhiyun nand->dev_ready = plat_dev_ready; 61*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun return 0; 64*4882a593Smuzhiyun } 65