1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * NXP GPMI NAND flash driver (DT initialization)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2018 Toradex
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Stefan Agner <stefan.agner@toradex.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Based on denali_dt.c
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dm.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/ioport.h>
16*4882a593Smuzhiyun #include <linux/printk.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "mxs_nand.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct mxs_nand_dt_data {
21*4882a593Smuzhiyun unsigned int max_ecc_strength_supported;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
25*4882a593Smuzhiyun .max_ecc_strength_supported = 40,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
29*4882a593Smuzhiyun .max_ecc_strength_supported = 62,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct udevice_id mxs_nand_dt_ids[] = {
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun .compatible = "fsl,imx6q-gpmi-nand",
35*4882a593Smuzhiyun .data = (unsigned long)&mxs_nand_imx6q_data,
36*4882a593Smuzhiyun },
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun .compatible = "fsl,imx7d-gpmi-nand",
39*4882a593Smuzhiyun .data = (unsigned long)&mxs_nand_imx7d_data,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun { /* sentinel */ }
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
mxs_nand_dt_probe(struct udevice * dev)44*4882a593Smuzhiyun static int mxs_nand_dt_probe(struct udevice *dev)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct mxs_nand_info *info = dev_get_priv(dev);
47*4882a593Smuzhiyun const struct mxs_nand_dt_data *data;
48*4882a593Smuzhiyun struct resource res;
49*4882a593Smuzhiyun int ret;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun data = (void *)dev_get_driver_data(dev);
52*4882a593Smuzhiyun if (data)
53*4882a593Smuzhiyun info->max_ecc_strength_supported = data->max_ecc_strength_supported;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun info->dev = dev;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
58*4882a593Smuzhiyun if (ret)
59*4882a593Smuzhiyun return ret;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = dev_read_resource_byname(dev, "bch", &res);
65*4882a593Smuzhiyun if (ret)
66*4882a593Smuzhiyun return ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return mxs_nand_init_ctrl(info);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun U_BOOT_DRIVER(mxs_nand_dt) = {
76*4882a593Smuzhiyun .name = "mxs-nand-dt",
77*4882a593Smuzhiyun .id = UCLASS_MTD,
78*4882a593Smuzhiyun .of_match = mxs_nand_dt_ids,
79*4882a593Smuzhiyun .probe = mxs_nand_dt_probe,
80*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct mxs_nand_info),
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
board_nand_init(void)83*4882a593Smuzhiyun void board_nand_init(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct udevice *dev;
86*4882a593Smuzhiyun int ret;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun ret = uclass_get_device_by_driver(UCLASS_MTD,
89*4882a593Smuzhiyun DM_GET_DRIVER(mxs_nand_dt),
90*4882a593Smuzhiyun &dev);
91*4882a593Smuzhiyun if (ret && ret != -ENODEV)
92*4882a593Smuzhiyun pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
93*4882a593Smuzhiyun ret);
94*4882a593Smuzhiyun }
95