1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/soc.h>
12*4882a593Smuzhiyun #include <asm/arch/mpp.h>
13*4882a593Smuzhiyun #include <nand.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* NAND Flash Soc registers */
16*4882a593Smuzhiyun struct kwnandf_registers {
17*4882a593Smuzhiyun u32 rd_params; /* 0x10418 */
18*4882a593Smuzhiyun u32 wr_param; /* 0x1041c */
19*4882a593Smuzhiyun u8 pad[0x10470 - 0x1041c - 4];
20*4882a593Smuzhiyun u32 ctrl; /* 0x10470 */
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static struct kwnandf_registers *nf_reg =
24*4882a593Smuzhiyun (struct kwnandf_registers *)KW_NANDF_BASE;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static u32 nand_mpp_backup[9] = { 0 };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * hardware specific access to control-lines/bits
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define NAND_ACTCEBOOT_BIT 0x02
32*4882a593Smuzhiyun
kw_nand_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)33*4882a593Smuzhiyun static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
34*4882a593Smuzhiyun unsigned int ctrl)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct nand_chip *nc = mtd_to_nand(mtd);
37*4882a593Smuzhiyun u32 offs;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (cmd == NAND_CMD_NONE)
40*4882a593Smuzhiyun return;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (ctrl & NAND_CLE)
43*4882a593Smuzhiyun offs = (1 << 0); /* Commands with A[1:0] == 01 */
44*4882a593Smuzhiyun else if (ctrl & NAND_ALE)
45*4882a593Smuzhiyun offs = (1 << 1); /* Addresses with A[1:0] == 10 */
46*4882a593Smuzhiyun else
47*4882a593Smuzhiyun return;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun writeb(cmd, nc->IO_ADDR_W + offs);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
kw_nand_select_chip(struct mtd_info * mtd,int chip)52*4882a593Smuzhiyun void kw_nand_select_chip(struct mtd_info *mtd, int chip)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 data;
55*4882a593Smuzhiyun static const u32 nand_config[] = {
56*4882a593Smuzhiyun MPP0_NF_IO2,
57*4882a593Smuzhiyun MPP1_NF_IO3,
58*4882a593Smuzhiyun MPP2_NF_IO4,
59*4882a593Smuzhiyun MPP3_NF_IO5,
60*4882a593Smuzhiyun MPP4_NF_IO6,
61*4882a593Smuzhiyun MPP5_NF_IO7,
62*4882a593Smuzhiyun MPP18_NF_IO0,
63*4882a593Smuzhiyun MPP19_NF_IO1,
64*4882a593Smuzhiyun 0
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (chip >= 0)
68*4882a593Smuzhiyun kirkwood_mpp_conf(nand_config, nand_mpp_backup);
69*4882a593Smuzhiyun else
70*4882a593Smuzhiyun kirkwood_mpp_conf(nand_mpp_backup, NULL);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun data = readl(&nf_reg->ctrl);
73*4882a593Smuzhiyun data |= NAND_ACTCEBOOT_BIT;
74*4882a593Smuzhiyun writel(data, &nf_reg->ctrl);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
board_nand_init(struct nand_chip * nand)77*4882a593Smuzhiyun int board_nand_init(struct nand_chip *nand)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
80*4882a593Smuzhiyun #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
81*4882a593Smuzhiyun nand->options |= NAND_NO_SUBPAGE_WRITE;
82*4882a593Smuzhiyun #endif
83*4882a593Smuzhiyun #if defined(CONFIG_NAND_ECC_BCH)
84*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT_BCH;
85*4882a593Smuzhiyun #else
86*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT;
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun nand->cmd_ctrl = kw_nand_hwcontrol;
89*4882a593Smuzhiyun nand->chip_delay = 40;
90*4882a593Smuzhiyun nand->select_chip = kw_nand_select_chip;
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93