1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
2 *
3 * Copyright (c) 2006-2008 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <malloc.h>
13 #include <nand.h>
14
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/nand_ecc.h>
18
19 #include <asm/io.h>
20 #include <linux/errno.h>
21
22 #ifdef VERBOSE_DEBUG
23 #define DEBUG_ELBC
24 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
25 #else
26 #define vdbg(format, arg...) do {} while (0)
27 #endif
28
29 /* Can't use plain old DEBUG because the linux mtd
30 * headers define it as a macro.
31 */
32 #ifdef DEBUG_ELBC
33 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
34 #else
35 #define dbg(format, arg...) do {} while (0)
36 #endif
37
38 #define MAX_BANKS 8
39 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
40
41 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
42
43 struct fsl_elbc_ctrl;
44
45 /* mtd information per set */
46
47 struct fsl_elbc_mtd {
48 struct nand_chip chip;
49 struct fsl_elbc_ctrl *ctrl;
50
51 struct device *dev;
52 int bank; /* Chip select bank number */
53 u8 __iomem *vbase; /* Chip select base virtual address */
54 int page_size; /* NAND page size (0=512, 1=2048) */
55 unsigned int fmr; /* FCM Flash Mode Register value */
56 };
57
58 /* overview of the fsl elbc controller */
59
60 struct fsl_elbc_ctrl {
61 struct nand_hw_control controller;
62 struct fsl_elbc_mtd *chips[MAX_BANKS];
63
64 /* device info */
65 fsl_lbc_t *regs;
66 u8 __iomem *addr; /* Address of assigned FCM buffer */
67 unsigned int page; /* Last page written to / read from */
68 unsigned int read_bytes; /* Number of bytes read during command */
69 unsigned int column; /* Saved column from SEQIN */
70 unsigned int index; /* Pointer to next byte to 'read' */
71 unsigned int status; /* status read from LTESR after last op */
72 unsigned int mdr; /* UPM/FCM Data Register value */
73 unsigned int use_mdr; /* Non zero if the MDR is to be set */
74 unsigned int oob; /* Non zero if operating on OOB data */
75 };
76
77 /* These map to the positions used by the FCM hardware ECC generator */
78
79 /* Small Page FLASH with FMR[ECCM] = 0 */
80 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
81 .eccbytes = 3,
82 .eccpos = {6, 7, 8},
83 .oobfree = { {0, 5}, {9, 7} },
84 };
85
86 /* Small Page FLASH with FMR[ECCM] = 1 */
87 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
88 .eccbytes = 3,
89 .eccpos = {8, 9, 10},
90 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
91 };
92
93 /* Large Page FLASH with FMR[ECCM] = 0 */
94 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
95 .eccbytes = 12,
96 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
97 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
98 };
99
100 /* Large Page FLASH with FMR[ECCM] = 1 */
101 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
102 .eccbytes = 12,
103 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
104 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
105 };
106
107 /*
108 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
109 * 1, so we have to adjust bad block pattern. This pattern should be used for
110 * x8 chips only. So far hardware does not support x16 chips anyway.
111 */
112 static u8 scan_ff_pattern[] = { 0xff, };
113
114 static struct nand_bbt_descr largepage_memorybased = {
115 .options = 0,
116 .offs = 0,
117 .len = 1,
118 .pattern = scan_ff_pattern,
119 };
120
121 /*
122 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
123 * interfere with ECC positions, that's why we implement our own descriptors.
124 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
125 */
126 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
127 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
128
129 static struct nand_bbt_descr bbt_main_descr = {
130 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
131 NAND_BBT_2BIT | NAND_BBT_VERSION,
132 .offs = 11,
133 .len = 4,
134 .veroffs = 15,
135 .maxblocks = 4,
136 .pattern = bbt_pattern,
137 };
138
139 static struct nand_bbt_descr bbt_mirror_descr = {
140 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
141 NAND_BBT_2BIT | NAND_BBT_VERSION,
142 .offs = 11,
143 .len = 4,
144 .veroffs = 15,
145 .maxblocks = 4,
146 .pattern = mirror_pattern,
147 };
148
149 /*=================================*/
150
151 /*
152 * Set up the FCM hardware block and page address fields, and the fcm
153 * structure addr field to point to the correct FCM buffer in memory
154 */
set_addr(struct mtd_info * mtd,int column,int page_addr,int oob)155 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
156 {
157 struct nand_chip *chip = mtd_to_nand(mtd);
158 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
159 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
160 fsl_lbc_t *lbc = ctrl->regs;
161 int buf_num;
162
163 ctrl->page = page_addr;
164
165 if (priv->page_size) {
166 out_be32(&lbc->fbar, page_addr >> 6);
167 out_be32(&lbc->fpar,
168 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
169 (oob ? FPAR_LP_MS : 0) | column);
170 buf_num = (page_addr & 1) << 2;
171 } else {
172 out_be32(&lbc->fbar, page_addr >> 5);
173 out_be32(&lbc->fpar,
174 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
175 (oob ? FPAR_SP_MS : 0) | column);
176 buf_num = page_addr & 7;
177 }
178
179 ctrl->addr = priv->vbase + buf_num * 1024;
180 ctrl->index = column;
181
182 /* for OOB data point to the second half of the buffer */
183 if (oob)
184 ctrl->index += priv->page_size ? 2048 : 512;
185
186 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
187 "index %x, pes %d ps %d\n",
188 buf_num, ctrl->addr, priv->vbase, ctrl->index,
189 chip->phys_erase_shift, chip->page_shift);
190 }
191
192 /*
193 * execute FCM command and wait for it to complete
194 */
fsl_elbc_run_command(struct mtd_info * mtd)195 static int fsl_elbc_run_command(struct mtd_info *mtd)
196 {
197 struct nand_chip *chip = mtd_to_nand(mtd);
198 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
199 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
200 fsl_lbc_t *lbc = ctrl->regs;
201 u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
202 u32 time_start;
203 u32 ltesr;
204
205 /* Setup the FMR[OP] to execute without write protection */
206 out_be32(&lbc->fmr, priv->fmr | 3);
207 if (ctrl->use_mdr)
208 out_be32(&lbc->mdr, ctrl->mdr);
209
210 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
211 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
212 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
213 "fbcr=%08x bank=%d\n",
214 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
215 in_be32(&lbc->fbcr), priv->bank);
216
217 /* execute special operation */
218 out_be32(&lbc->lsor, priv->bank);
219
220 /* wait for FCM complete flag or timeout */
221 time_start = get_timer(0);
222
223 ltesr = 0;
224 while (get_timer(time_start) < timeo) {
225 ltesr = in_be32(&lbc->ltesr);
226 if (ltesr & LTESR_CC)
227 break;
228 }
229
230 ctrl->status = ltesr & LTESR_NAND_MASK;
231 out_be32(&lbc->ltesr, ctrl->status);
232 out_be32(&lbc->lteatr, 0);
233
234 /* store mdr value in case it was needed */
235 if (ctrl->use_mdr)
236 ctrl->mdr = in_be32(&lbc->mdr);
237
238 ctrl->use_mdr = 0;
239
240 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
241 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
242
243 /* returns 0 on success otherwise non-zero) */
244 return ctrl->status == LTESR_CC ? 0 : -EIO;
245 }
246
fsl_elbc_do_read(struct nand_chip * chip,int oob)247 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
248 {
249 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
250 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
251 fsl_lbc_t *lbc = ctrl->regs;
252
253 if (priv->page_size) {
254 out_be32(&lbc->fir,
255 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
256 (FIR_OP_CA << FIR_OP1_SHIFT) |
257 (FIR_OP_PA << FIR_OP2_SHIFT) |
258 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
259 (FIR_OP_RBW << FIR_OP4_SHIFT));
260
261 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
262 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
263 } else {
264 out_be32(&lbc->fir,
265 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
266 (FIR_OP_CA << FIR_OP1_SHIFT) |
267 (FIR_OP_PA << FIR_OP2_SHIFT) |
268 (FIR_OP_RBW << FIR_OP3_SHIFT));
269
270 if (oob)
271 out_be32(&lbc->fcr,
272 NAND_CMD_READOOB << FCR_CMD0_SHIFT);
273 else
274 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
275 }
276 }
277
278 /* cmdfunc send commands to the FCM */
fsl_elbc_cmdfunc(struct mtd_info * mtd,unsigned int command,int column,int page_addr)279 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
280 int column, int page_addr)
281 {
282 struct nand_chip *chip = mtd_to_nand(mtd);
283 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
284 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
285 fsl_lbc_t *lbc = ctrl->regs;
286
287 ctrl->use_mdr = 0;
288
289 /* clear the read buffer */
290 ctrl->read_bytes = 0;
291 if (command != NAND_CMD_PAGEPROG)
292 ctrl->index = 0;
293
294 switch (command) {
295 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
296 case NAND_CMD_READ1:
297 column += 256;
298
299 /* fall-through */
300 case NAND_CMD_READ0:
301 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
302 " 0x%x, column: 0x%x.\n", page_addr, column);
303
304 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
305 set_addr(mtd, 0, page_addr, 0);
306
307 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
308 ctrl->index += column;
309
310 fsl_elbc_do_read(chip, 0);
311 fsl_elbc_run_command(mtd);
312 return;
313
314 /* READOOB reads only the OOB because no ECC is performed. */
315 case NAND_CMD_READOOB:
316 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
317 " 0x%x, column: 0x%x.\n", page_addr, column);
318
319 out_be32(&lbc->fbcr, mtd->oobsize - column);
320 set_addr(mtd, column, page_addr, 1);
321
322 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
323
324 fsl_elbc_do_read(chip, 1);
325 fsl_elbc_run_command(mtd);
326
327 return;
328
329 /* READID must read all 5 possible bytes while CEB is active */
330 case NAND_CMD_READID:
331 case NAND_CMD_PARAM:
332 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
333
334 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
335 (FIR_OP_UA << FIR_OP1_SHIFT) |
336 (FIR_OP_RBW << FIR_OP2_SHIFT));
337 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
338 /*
339 * although currently it's 8 bytes for READID, we always read
340 * the maximum 256 bytes(for PARAM)
341 */
342 out_be32(&lbc->fbcr, 256);
343 ctrl->read_bytes = 256;
344 ctrl->use_mdr = 1;
345 ctrl->mdr = column;
346 set_addr(mtd, 0, 0, 0);
347 fsl_elbc_run_command(mtd);
348 return;
349
350 /* ERASE1 stores the block and page address */
351 case NAND_CMD_ERASE1:
352 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
353 "page_addr: 0x%x.\n", page_addr);
354 set_addr(mtd, 0, page_addr, 0);
355 return;
356
357 /* ERASE2 uses the block and page address from ERASE1 */
358 case NAND_CMD_ERASE2:
359 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
360
361 out_be32(&lbc->fir,
362 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
363 (FIR_OP_PA << FIR_OP1_SHIFT) |
364 (FIR_OP_CM1 << FIR_OP2_SHIFT));
365
366 out_be32(&lbc->fcr,
367 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
368 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
369
370 out_be32(&lbc->fbcr, 0);
371 ctrl->read_bytes = 0;
372
373 fsl_elbc_run_command(mtd);
374 return;
375
376 /* SEQIN sets up the addr buffer and all registers except the length */
377 case NAND_CMD_SEQIN: {
378 u32 fcr;
379 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
380 "page_addr: 0x%x, column: 0x%x.\n",
381 page_addr, column);
382
383 ctrl->column = column;
384 ctrl->oob = 0;
385
386 if (priv->page_size) {
387 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
388 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
389
390 out_be32(&lbc->fir,
391 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
392 (FIR_OP_CA << FIR_OP1_SHIFT) |
393 (FIR_OP_PA << FIR_OP2_SHIFT) |
394 (FIR_OP_WB << FIR_OP3_SHIFT) |
395 (FIR_OP_CW1 << FIR_OP4_SHIFT));
396 } else {
397 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
398 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
399
400 out_be32(&lbc->fir,
401 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
402 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
403 (FIR_OP_CA << FIR_OP2_SHIFT) |
404 (FIR_OP_PA << FIR_OP3_SHIFT) |
405 (FIR_OP_WB << FIR_OP4_SHIFT) |
406 (FIR_OP_CW1 << FIR_OP5_SHIFT));
407
408 if (column >= mtd->writesize) {
409 /* OOB area --> READOOB */
410 column -= mtd->writesize;
411 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
412 ctrl->oob = 1;
413 } else if (column < 256) {
414 /* First 256 bytes --> READ0 */
415 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
416 } else {
417 /* Second 256 bytes --> READ1 */
418 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
419 }
420 }
421
422 out_be32(&lbc->fcr, fcr);
423 set_addr(mtd, column, page_addr, ctrl->oob);
424 return;
425 }
426
427 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
428 case NAND_CMD_PAGEPROG: {
429 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
430 "writing %d bytes.\n", ctrl->index);
431
432 /* if the write did not start at 0 or is not a full page
433 * then set the exact length, otherwise use a full page
434 * write so the HW generates the ECC.
435 */
436 if (ctrl->oob || ctrl->column != 0 ||
437 ctrl->index != mtd->writesize + mtd->oobsize)
438 out_be32(&lbc->fbcr, ctrl->index);
439 else
440 out_be32(&lbc->fbcr, 0);
441
442 fsl_elbc_run_command(mtd);
443
444 return;
445 }
446
447 /* CMD_STATUS must read the status byte while CEB is active */
448 /* Note - it does not wait for the ready line */
449 case NAND_CMD_STATUS:
450 out_be32(&lbc->fir,
451 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
452 (FIR_OP_RBW << FIR_OP1_SHIFT));
453 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
454 out_be32(&lbc->fbcr, 1);
455 set_addr(mtd, 0, 0, 0);
456 ctrl->read_bytes = 1;
457
458 fsl_elbc_run_command(mtd);
459
460 /* The chip always seems to report that it is
461 * write-protected, even when it is not.
462 */
463 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
464 return;
465
466 /* RESET without waiting for the ready line */
467 case NAND_CMD_RESET:
468 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
469 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
470 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
471 fsl_elbc_run_command(mtd);
472 return;
473
474 default:
475 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
476 command);
477 }
478 }
479
fsl_elbc_select_chip(struct mtd_info * mtd,int chip)480 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
481 {
482 /* The hardware does not seem to support multiple
483 * chips per bank.
484 */
485 }
486
487 /*
488 * Write buf to the FCM Controller Data Buffer
489 */
fsl_elbc_write_buf(struct mtd_info * mtd,const u8 * buf,int len)490 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
491 {
492 struct nand_chip *chip = mtd_to_nand(mtd);
493 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
494 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
495 unsigned int bufsize = mtd->writesize + mtd->oobsize;
496
497 if (len <= 0) {
498 printf("write_buf of %d bytes", len);
499 ctrl->status = 0;
500 return;
501 }
502
503 if ((unsigned int)len > bufsize - ctrl->index) {
504 printf("write_buf beyond end of buffer "
505 "(%d requested, %u available)\n",
506 len, bufsize - ctrl->index);
507 len = bufsize - ctrl->index;
508 }
509
510 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
511 /*
512 * This is workaround for the weird elbc hangs during nand write,
513 * Scott Wood says: "...perhaps difference in how long it takes a
514 * write to make it through the localbus compared to a write to IMMR
515 * is causing problems, and sync isn't helping for some reason."
516 * Reading back the last byte helps though.
517 */
518 in_8(&ctrl->addr[ctrl->index] + len - 1);
519
520 ctrl->index += len;
521 }
522
523 /*
524 * read a byte from either the FCM hardware buffer if it has any data left
525 * otherwise issue a command to read a single byte.
526 */
fsl_elbc_read_byte(struct mtd_info * mtd)527 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
528 {
529 struct nand_chip *chip = mtd_to_nand(mtd);
530 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
531 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
532
533 /* If there are still bytes in the FCM, then use the next byte. */
534 if (ctrl->index < ctrl->read_bytes)
535 return in_8(&ctrl->addr[ctrl->index++]);
536
537 printf("read_byte beyond end of buffer\n");
538 return ERR_BYTE;
539 }
540
541 /*
542 * Read from the FCM Controller Data Buffer
543 */
fsl_elbc_read_buf(struct mtd_info * mtd,u8 * buf,int len)544 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
545 {
546 struct nand_chip *chip = mtd_to_nand(mtd);
547 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
548 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
549 int avail;
550
551 if (len < 0)
552 return;
553
554 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
555 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
556 ctrl->index += avail;
557
558 if (len > avail)
559 printf("read_buf beyond end of buffer "
560 "(%d requested, %d available)\n",
561 len, avail);
562 }
563
564 /* This function is called after Program and Erase Operations to
565 * check for success or failure.
566 */
fsl_elbc_wait(struct mtd_info * mtd,struct nand_chip * chip)567 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
568 {
569 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
570 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
571 fsl_lbc_t *lbc = ctrl->regs;
572
573 if (ctrl->status != LTESR_CC)
574 return NAND_STATUS_FAIL;
575
576 /* Use READ_STATUS command, but wait for the device to be ready */
577 ctrl->use_mdr = 0;
578 out_be32(&lbc->fir,
579 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
580 (FIR_OP_RBW << FIR_OP1_SHIFT));
581 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
582 out_be32(&lbc->fbcr, 1);
583 set_addr(mtd, 0, 0, 0);
584 ctrl->read_bytes = 1;
585
586 fsl_elbc_run_command(mtd);
587
588 if (ctrl->status != LTESR_CC)
589 return NAND_STATUS_FAIL;
590
591 /* The chip always seems to report that it is
592 * write-protected, even when it is not.
593 */
594 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
595 return fsl_elbc_read_byte(mtd);
596 }
597
fsl_elbc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)598 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
599 uint8_t *buf, int oob_required, int page)
600 {
601 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
602 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
603
604 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
605 mtd->ecc_stats.failed++;
606
607 return 0;
608 }
609
610 /* ECC will be calculated automatically, and errors will be detected in
611 * waitfunc.
612 */
fsl_elbc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)613 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
614 const uint8_t *buf, int oob_required,
615 int page)
616 {
617 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
618 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
619
620 return 0;
621 }
622
623 static struct fsl_elbc_ctrl *elbc_ctrl;
624
625 /* ECC will be calculated automatically, and errors will be detected in
626 * waitfunc.
627 */
fsl_elbc_write_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)628 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
629 uint32_t offset, uint32_t data_len,
630 const uint8_t *buf, int oob_required, int page)
631 {
632 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
633 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
634
635 return 0;
636 }
637
fsl_elbc_ctrl_init(void)638 static void fsl_elbc_ctrl_init(void)
639 {
640 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
641 if (!elbc_ctrl)
642 return;
643
644 elbc_ctrl->regs = LBC_BASE_ADDR;
645
646 /* clear event registers */
647 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
648 out_be32(&elbc_ctrl->regs->lteatr, 0);
649
650 /* Enable interrupts for any detected events */
651 out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
652
653 elbc_ctrl->read_bytes = 0;
654 elbc_ctrl->index = 0;
655 elbc_ctrl->addr = NULL;
656 }
657
fsl_elbc_chip_init(int devnum,u8 * addr)658 static int fsl_elbc_chip_init(int devnum, u8 *addr)
659 {
660 struct mtd_info *mtd;
661 struct nand_chip *nand;
662 struct fsl_elbc_mtd *priv;
663 uint32_t br = 0, or = 0;
664 int ret;
665
666 if (!elbc_ctrl) {
667 fsl_elbc_ctrl_init();
668 if (!elbc_ctrl)
669 return -1;
670 }
671
672 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
673 if (!priv)
674 return -ENOMEM;
675
676 priv->ctrl = elbc_ctrl;
677 priv->vbase = addr;
678
679 /* Find which chip select it is connected to. It'd be nice
680 * if we could pass more than one datum to the NAND driver...
681 */
682 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
683 phys_addr_t phys_addr = virt_to_phys(addr);
684
685 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
686 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
687
688 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
689 (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
690 break;
691 }
692
693 if (priv->bank >= MAX_BANKS) {
694 printf("fsl_elbc_nand: address did not match any "
695 "chip selects\n");
696 kfree(priv);
697 return -ENODEV;
698 }
699
700 nand = &priv->chip;
701 mtd = nand_to_mtd(nand);
702
703 elbc_ctrl->chips[priv->bank] = priv;
704
705 /* fill in nand_chip structure */
706 /* set up function call table */
707 nand->read_byte = fsl_elbc_read_byte;
708 nand->write_buf = fsl_elbc_write_buf;
709 nand->read_buf = fsl_elbc_read_buf;
710 nand->select_chip = fsl_elbc_select_chip;
711 nand->cmdfunc = fsl_elbc_cmdfunc;
712 nand->waitfunc = fsl_elbc_wait;
713
714 /* set up nand options */
715 nand->bbt_td = &bbt_main_descr;
716 nand->bbt_md = &bbt_mirror_descr;
717
718 /* set up nand options */
719 nand->options = NAND_NO_SUBPAGE_WRITE;
720 nand->bbt_options = NAND_BBT_USE_FLASH;
721
722 nand->controller = &elbc_ctrl->controller;
723 nand_set_controller_data(nand, priv);
724
725 nand->ecc.read_page = fsl_elbc_read_page;
726 nand->ecc.write_page = fsl_elbc_write_page;
727 nand->ecc.write_subpage = fsl_elbc_write_subpage;
728
729 priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
730
731 /* If CS Base Register selects full hardware ECC then use it */
732 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
733 nand->ecc.mode = NAND_ECC_HW;
734
735 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
736 &fsl_elbc_oob_sp_eccm1 :
737 &fsl_elbc_oob_sp_eccm0;
738
739 nand->ecc.size = 512;
740 nand->ecc.bytes = 3;
741 nand->ecc.steps = 1;
742 nand->ecc.strength = 1;
743 } else {
744 /* otherwise fall back to software ECC */
745 #if defined(CONFIG_NAND_ECC_BCH)
746 nand->ecc.mode = NAND_ECC_SOFT_BCH;
747 #else
748 nand->ecc.mode = NAND_ECC_SOFT;
749 #endif
750 }
751
752 ret = nand_scan_ident(mtd, 1, NULL);
753 if (ret)
754 return ret;
755
756 /* Large-page-specific setup */
757 if (mtd->writesize == 2048) {
758 setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
759 OR_FCM_PGS);
760 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
761
762 priv->page_size = 1;
763 nand->badblock_pattern = &largepage_memorybased;
764
765 /*
766 * Hardware expects small page has ECCM0, large page has
767 * ECCM1 when booting from NAND, and we follow that even
768 * when not booting from NAND.
769 */
770 priv->fmr |= FMR_ECCM;
771
772 /* adjust ecc setup if needed */
773 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
774 nand->ecc.steps = 4;
775 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
776 &fsl_elbc_oob_lp_eccm1 :
777 &fsl_elbc_oob_lp_eccm0;
778 }
779 } else if (mtd->writesize == 512) {
780 clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
781 OR_FCM_PGS);
782 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
783 } else {
784 return -ENODEV;
785 }
786
787 ret = nand_scan_tail(mtd);
788 if (ret)
789 return ret;
790
791 ret = nand_register(devnum, mtd);
792 if (ret)
793 return ret;
794
795 return 0;
796 }
797
798 #ifndef CONFIG_SYS_NAND_BASE_LIST
799 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
800 #endif
801
802 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
803 CONFIG_SYS_NAND_BASE_LIST;
804
board_nand_init(void)805 void board_nand_init(void)
806 {
807 int i;
808
809 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
810 fsl_elbc_chip_init(i, (u8 *)base_address[i]);
811 }
812