1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright © 2010-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <common.h>
16 #include <asm/io.h>
17 #include <memalign.h>
18 #include <nand.h>
19 #include <clk.h>
20 #include <linux/ioport.h>
21 #include <linux/completion.h>
22 #include <linux/errno.h>
23 #include <linux/log2.h>
24 #include <asm/processor.h>
25 #include <dm.h>
26
27 #include "brcmnand.h"
28 #include "brcmnand_compat.h"
29
30 /*
31 * This flag controls if WP stays on between erase/write commands to mitigate
32 * flash corruption due to power glitches. Values:
33 * 0: NAND_WP is not used or not available
34 * 1: NAND_WP is set by default, cleared for erase/write operations
35 * 2: NAND_WP is always cleared
36 */
37 static int wp_on = 1;
38 module_param(wp_on, int, 0444);
39
40 /***********************************************************************
41 * Definitions
42 ***********************************************************************/
43
44 #define DRV_NAME "brcmnand"
45
46 #define CMD_NULL 0x00
47 #define CMD_PAGE_READ 0x01
48 #define CMD_SPARE_AREA_READ 0x02
49 #define CMD_STATUS_READ 0x03
50 #define CMD_PROGRAM_PAGE 0x04
51 #define CMD_PROGRAM_SPARE_AREA 0x05
52 #define CMD_COPY_BACK 0x06
53 #define CMD_DEVICE_ID_READ 0x07
54 #define CMD_BLOCK_ERASE 0x08
55 #define CMD_FLASH_RESET 0x09
56 #define CMD_BLOCKS_LOCK 0x0a
57 #define CMD_BLOCKS_LOCK_DOWN 0x0b
58 #define CMD_BLOCKS_UNLOCK 0x0c
59 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
60 #define CMD_PARAMETER_READ 0x0e
61 #define CMD_PARAMETER_CHANGE_COL 0x0f
62 #define CMD_LOW_LEVEL_OP 0x10
63
64 struct brcm_nand_dma_desc {
65 u32 next_desc;
66 u32 next_desc_ext;
67 u32 cmd_irq;
68 u32 dram_addr;
69 u32 dram_addr_ext;
70 u32 tfr_len;
71 u32 total_len;
72 u32 flash_addr;
73 u32 flash_addr_ext;
74 u32 cs;
75 u32 pad2[5];
76 u32 status_valid;
77 } __packed;
78
79 /* Bitfields for brcm_nand_dma_desc::status_valid */
80 #define FLASH_DMA_ECC_ERROR (1 << 8)
81 #define FLASH_DMA_CORR_ERROR (1 << 9)
82
83 /* 512B flash cache in the NAND controller HW */
84 #define FC_SHIFT 9U
85 #define FC_BYTES 512U
86 #define FC_WORDS (FC_BYTES >> 2)
87
88 #define BRCMNAND_MIN_PAGESIZE 512
89 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
90 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
91
92 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
93 #define NAND_POLL_STATUS_TIMEOUT_MS 100
94
95 /* Controller feature flags */
96 enum {
97 BRCMNAND_HAS_1K_SECTORS = BIT(0),
98 BRCMNAND_HAS_PREFETCH = BIT(1),
99 BRCMNAND_HAS_CACHE_MODE = BIT(2),
100 BRCMNAND_HAS_WP = BIT(3),
101 };
102
103 struct brcmnand_controller {
104 #ifndef __UBOOT__
105 struct device *dev;
106 #else
107 struct udevice *dev;
108 #endif /* __UBOOT__ */
109 struct nand_hw_control controller;
110 void __iomem *nand_base;
111 void __iomem *nand_fc; /* flash cache */
112 void __iomem *flash_dma_base;
113 unsigned int irq;
114 unsigned int dma_irq;
115 int nand_version;
116 int parameter_page_big_endian;
117
118 /* Some SoCs provide custom interrupt status register(s) */
119 struct brcmnand_soc *soc;
120
121 /* Some SoCs have a gateable clock for the controller */
122 struct clk *clk;
123
124 int cmd_pending;
125 bool dma_pending;
126 struct completion done;
127 struct completion dma_done;
128
129 /* List of NAND hosts (one for each chip-select) */
130 struct list_head host_list;
131
132 struct brcm_nand_dma_desc *dma_desc;
133 dma_addr_t dma_pa;
134
135 /* in-memory cache of the FLASH_CACHE, used only for some commands */
136 u8 flash_cache[FC_BYTES];
137
138 /* Controller revision details */
139 const u16 *reg_offsets;
140 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
141 const u8 *cs_offsets; /* within each chip-select */
142 const u8 *cs0_offsets; /* within CS0, if different */
143 unsigned int max_block_size;
144 const unsigned int *block_sizes;
145 unsigned int max_page_size;
146 const unsigned int *page_sizes;
147 unsigned int max_oob;
148 u32 features;
149
150 /* for low-power standby/resume only */
151 u32 nand_cs_nand_select;
152 u32 nand_cs_nand_xor;
153 u32 corr_stat_threshold;
154 u32 flash_dma_mode;
155 };
156
157 struct brcmnand_cfg {
158 u64 device_size;
159 unsigned int block_size;
160 unsigned int page_size;
161 unsigned int spare_area_size;
162 unsigned int device_width;
163 unsigned int col_adr_bytes;
164 unsigned int blk_adr_bytes;
165 unsigned int ful_adr_bytes;
166 unsigned int sector_size_1k;
167 unsigned int ecc_level;
168 /* use for low-power standby/resume only */
169 u32 acc_control;
170 u32 config;
171 u32 config_ext;
172 u32 timing_1;
173 u32 timing_2;
174 };
175
176 struct brcmnand_host {
177 struct list_head node;
178
179 struct nand_chip chip;
180 #ifndef __UBOOT__
181 struct platform_device *pdev;
182 #else
183 struct udevice *pdev;
184 #endif /* __UBOOT__ */
185 int cs;
186
187 unsigned int last_cmd;
188 unsigned int last_byte;
189 u64 last_addr;
190 struct brcmnand_cfg hwcfg;
191 struct brcmnand_controller *ctrl;
192 };
193
194 enum brcmnand_reg {
195 BRCMNAND_CMD_START = 0,
196 BRCMNAND_CMD_EXT_ADDRESS,
197 BRCMNAND_CMD_ADDRESS,
198 BRCMNAND_INTFC_STATUS,
199 BRCMNAND_CS_SELECT,
200 BRCMNAND_CS_XOR,
201 BRCMNAND_LL_OP,
202 BRCMNAND_CS0_BASE,
203 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
204 BRCMNAND_CORR_THRESHOLD,
205 BRCMNAND_CORR_THRESHOLD_EXT,
206 BRCMNAND_UNCORR_COUNT,
207 BRCMNAND_CORR_COUNT,
208 BRCMNAND_CORR_EXT_ADDR,
209 BRCMNAND_CORR_ADDR,
210 BRCMNAND_UNCORR_EXT_ADDR,
211 BRCMNAND_UNCORR_ADDR,
212 BRCMNAND_SEMAPHORE,
213 BRCMNAND_ID,
214 BRCMNAND_ID_EXT,
215 BRCMNAND_LL_RDATA,
216 BRCMNAND_OOB_READ_BASE,
217 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
218 BRCMNAND_OOB_WRITE_BASE,
219 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
220 BRCMNAND_FC_BASE,
221 };
222
223 /* BRCMNAND v4.0 */
224 static const u16 brcmnand_regs_v40[] = {
225 [BRCMNAND_CMD_START] = 0x04,
226 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
227 [BRCMNAND_CMD_ADDRESS] = 0x0c,
228 [BRCMNAND_INTFC_STATUS] = 0x6c,
229 [BRCMNAND_CS_SELECT] = 0x14,
230 [BRCMNAND_CS_XOR] = 0x18,
231 [BRCMNAND_LL_OP] = 0x178,
232 [BRCMNAND_CS0_BASE] = 0x40,
233 [BRCMNAND_CS1_BASE] = 0xd0,
234 [BRCMNAND_CORR_THRESHOLD] = 0x84,
235 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
236 [BRCMNAND_UNCORR_COUNT] = 0,
237 [BRCMNAND_CORR_COUNT] = 0,
238 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
239 [BRCMNAND_CORR_ADDR] = 0x74,
240 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
241 [BRCMNAND_UNCORR_ADDR] = 0x7c,
242 [BRCMNAND_SEMAPHORE] = 0x58,
243 [BRCMNAND_ID] = 0x60,
244 [BRCMNAND_ID_EXT] = 0x64,
245 [BRCMNAND_LL_RDATA] = 0x17c,
246 [BRCMNAND_OOB_READ_BASE] = 0x20,
247 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
248 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
249 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
250 [BRCMNAND_FC_BASE] = 0x200,
251 };
252
253 /* BRCMNAND v5.0 */
254 static const u16 brcmnand_regs_v50[] = {
255 [BRCMNAND_CMD_START] = 0x04,
256 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
257 [BRCMNAND_CMD_ADDRESS] = 0x0c,
258 [BRCMNAND_INTFC_STATUS] = 0x6c,
259 [BRCMNAND_CS_SELECT] = 0x14,
260 [BRCMNAND_CS_XOR] = 0x18,
261 [BRCMNAND_LL_OP] = 0x178,
262 [BRCMNAND_CS0_BASE] = 0x40,
263 [BRCMNAND_CS1_BASE] = 0xd0,
264 [BRCMNAND_CORR_THRESHOLD] = 0x84,
265 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
266 [BRCMNAND_UNCORR_COUNT] = 0,
267 [BRCMNAND_CORR_COUNT] = 0,
268 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
269 [BRCMNAND_CORR_ADDR] = 0x74,
270 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
271 [BRCMNAND_UNCORR_ADDR] = 0x7c,
272 [BRCMNAND_SEMAPHORE] = 0x58,
273 [BRCMNAND_ID] = 0x60,
274 [BRCMNAND_ID_EXT] = 0x64,
275 [BRCMNAND_LL_RDATA] = 0x17c,
276 [BRCMNAND_OOB_READ_BASE] = 0x20,
277 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
278 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
279 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
280 [BRCMNAND_FC_BASE] = 0x200,
281 };
282
283 /* BRCMNAND v6.0 - v7.1 */
284 static const u16 brcmnand_regs_v60[] = {
285 [BRCMNAND_CMD_START] = 0x04,
286 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
287 [BRCMNAND_CMD_ADDRESS] = 0x0c,
288 [BRCMNAND_INTFC_STATUS] = 0x14,
289 [BRCMNAND_CS_SELECT] = 0x18,
290 [BRCMNAND_CS_XOR] = 0x1c,
291 [BRCMNAND_LL_OP] = 0x20,
292 [BRCMNAND_CS0_BASE] = 0x50,
293 [BRCMNAND_CS1_BASE] = 0,
294 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
295 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
296 [BRCMNAND_UNCORR_COUNT] = 0xfc,
297 [BRCMNAND_CORR_COUNT] = 0x100,
298 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
299 [BRCMNAND_CORR_ADDR] = 0x110,
300 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
301 [BRCMNAND_UNCORR_ADDR] = 0x118,
302 [BRCMNAND_SEMAPHORE] = 0x150,
303 [BRCMNAND_ID] = 0x194,
304 [BRCMNAND_ID_EXT] = 0x198,
305 [BRCMNAND_LL_RDATA] = 0x19c,
306 [BRCMNAND_OOB_READ_BASE] = 0x200,
307 [BRCMNAND_OOB_READ_10_BASE] = 0,
308 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
309 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
310 [BRCMNAND_FC_BASE] = 0x400,
311 };
312
313 /* BRCMNAND v7.1 */
314 static const u16 brcmnand_regs_v71[] = {
315 [BRCMNAND_CMD_START] = 0x04,
316 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
317 [BRCMNAND_CMD_ADDRESS] = 0x0c,
318 [BRCMNAND_INTFC_STATUS] = 0x14,
319 [BRCMNAND_CS_SELECT] = 0x18,
320 [BRCMNAND_CS_XOR] = 0x1c,
321 [BRCMNAND_LL_OP] = 0x20,
322 [BRCMNAND_CS0_BASE] = 0x50,
323 [BRCMNAND_CS1_BASE] = 0,
324 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
325 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
326 [BRCMNAND_UNCORR_COUNT] = 0xfc,
327 [BRCMNAND_CORR_COUNT] = 0x100,
328 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
329 [BRCMNAND_CORR_ADDR] = 0x110,
330 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
331 [BRCMNAND_UNCORR_ADDR] = 0x118,
332 [BRCMNAND_SEMAPHORE] = 0x150,
333 [BRCMNAND_ID] = 0x194,
334 [BRCMNAND_ID_EXT] = 0x198,
335 [BRCMNAND_LL_RDATA] = 0x19c,
336 [BRCMNAND_OOB_READ_BASE] = 0x200,
337 [BRCMNAND_OOB_READ_10_BASE] = 0,
338 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
339 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
340 [BRCMNAND_FC_BASE] = 0x400,
341 };
342
343 /* BRCMNAND v7.2 */
344 static const u16 brcmnand_regs_v72[] = {
345 [BRCMNAND_CMD_START] = 0x04,
346 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
347 [BRCMNAND_CMD_ADDRESS] = 0x0c,
348 [BRCMNAND_INTFC_STATUS] = 0x14,
349 [BRCMNAND_CS_SELECT] = 0x18,
350 [BRCMNAND_CS_XOR] = 0x1c,
351 [BRCMNAND_LL_OP] = 0x20,
352 [BRCMNAND_CS0_BASE] = 0x50,
353 [BRCMNAND_CS1_BASE] = 0,
354 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
355 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
356 [BRCMNAND_UNCORR_COUNT] = 0xfc,
357 [BRCMNAND_CORR_COUNT] = 0x100,
358 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
359 [BRCMNAND_CORR_ADDR] = 0x110,
360 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
361 [BRCMNAND_UNCORR_ADDR] = 0x118,
362 [BRCMNAND_SEMAPHORE] = 0x150,
363 [BRCMNAND_ID] = 0x194,
364 [BRCMNAND_ID_EXT] = 0x198,
365 [BRCMNAND_LL_RDATA] = 0x19c,
366 [BRCMNAND_OOB_READ_BASE] = 0x200,
367 [BRCMNAND_OOB_READ_10_BASE] = 0,
368 [BRCMNAND_OOB_WRITE_BASE] = 0x400,
369 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
370 [BRCMNAND_FC_BASE] = 0x600,
371 };
372
373 enum brcmnand_cs_reg {
374 BRCMNAND_CS_CFG_EXT = 0,
375 BRCMNAND_CS_CFG,
376 BRCMNAND_CS_ACC_CONTROL,
377 BRCMNAND_CS_TIMING1,
378 BRCMNAND_CS_TIMING2,
379 };
380
381 /* Per chip-select offsets for v7.1 */
382 static const u8 brcmnand_cs_offsets_v71[] = {
383 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
384 [BRCMNAND_CS_CFG_EXT] = 0x04,
385 [BRCMNAND_CS_CFG] = 0x08,
386 [BRCMNAND_CS_TIMING1] = 0x0c,
387 [BRCMNAND_CS_TIMING2] = 0x10,
388 };
389
390 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
391 static const u8 brcmnand_cs_offsets[] = {
392 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
393 [BRCMNAND_CS_CFG_EXT] = 0x04,
394 [BRCMNAND_CS_CFG] = 0x04,
395 [BRCMNAND_CS_TIMING1] = 0x08,
396 [BRCMNAND_CS_TIMING2] = 0x0c,
397 };
398
399 /* Per chip-select offset for <= v5.0 on CS0 only */
400 static const u8 brcmnand_cs_offsets_cs0[] = {
401 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
402 [BRCMNAND_CS_CFG_EXT] = 0x08,
403 [BRCMNAND_CS_CFG] = 0x08,
404 [BRCMNAND_CS_TIMING1] = 0x10,
405 [BRCMNAND_CS_TIMING2] = 0x14,
406 };
407
408 /*
409 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
410 * one config register, but once the bitfields overflowed, newer controllers
411 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
412 */
413 enum {
414 CFG_BLK_ADR_BYTES_SHIFT = 8,
415 CFG_COL_ADR_BYTES_SHIFT = 12,
416 CFG_FUL_ADR_BYTES_SHIFT = 16,
417 CFG_BUS_WIDTH_SHIFT = 23,
418 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
419 CFG_DEVICE_SIZE_SHIFT = 24,
420
421 /* Only for pre-v7.1 (with no CFG_EXT register) */
422 CFG_PAGE_SIZE_SHIFT = 20,
423 CFG_BLK_SIZE_SHIFT = 28,
424
425 /* Only for v7.1+ (with CFG_EXT register) */
426 CFG_EXT_PAGE_SIZE_SHIFT = 0,
427 CFG_EXT_BLK_SIZE_SHIFT = 4,
428 };
429
430 /* BRCMNAND_INTFC_STATUS */
431 enum {
432 INTFC_FLASH_STATUS = GENMASK(7, 0),
433
434 INTFC_ERASED = BIT(27),
435 INTFC_OOB_VALID = BIT(28),
436 INTFC_CACHE_VALID = BIT(29),
437 INTFC_FLASH_READY = BIT(30),
438 INTFC_CTLR_READY = BIT(31),
439 };
440
nand_readreg(struct brcmnand_controller * ctrl,u32 offs)441 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
442 {
443 return brcmnand_readl(ctrl->nand_base + offs);
444 }
445
nand_writereg(struct brcmnand_controller * ctrl,u32 offs,u32 val)446 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
447 u32 val)
448 {
449 brcmnand_writel(val, ctrl->nand_base + offs);
450 }
451
brcmnand_revision_init(struct brcmnand_controller * ctrl)452 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
453 {
454 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
455 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
456 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
457
458 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
459
460 /* Only support v4.0+? */
461 if (ctrl->nand_version < 0x0400) {
462 dev_err(ctrl->dev, "version %#x not supported\n",
463 ctrl->nand_version);
464 return -ENODEV;
465 }
466
467 /* Register offsets */
468 if (ctrl->nand_version >= 0x0702)
469 ctrl->reg_offsets = brcmnand_regs_v72;
470 else if (ctrl->nand_version >= 0x0701)
471 ctrl->reg_offsets = brcmnand_regs_v71;
472 else if (ctrl->nand_version >= 0x0600)
473 ctrl->reg_offsets = brcmnand_regs_v60;
474 else if (ctrl->nand_version >= 0x0500)
475 ctrl->reg_offsets = brcmnand_regs_v50;
476 else if (ctrl->nand_version >= 0x0400)
477 ctrl->reg_offsets = brcmnand_regs_v40;
478
479 /* Chip-select stride */
480 if (ctrl->nand_version >= 0x0701)
481 ctrl->reg_spacing = 0x14;
482 else
483 ctrl->reg_spacing = 0x10;
484
485 /* Per chip-select registers */
486 if (ctrl->nand_version >= 0x0701) {
487 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
488 } else {
489 ctrl->cs_offsets = brcmnand_cs_offsets;
490
491 /* v5.0 and earlier has a different CS0 offset layout */
492 if (ctrl->nand_version <= 0x0500)
493 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
494 }
495
496 /* Page / block sizes */
497 if (ctrl->nand_version >= 0x0701) {
498 /* >= v7.1 use nice power-of-2 values! */
499 ctrl->max_page_size = 16 * 1024;
500 ctrl->max_block_size = 2 * 1024 * 1024;
501 } else {
502 ctrl->page_sizes = page_sizes;
503 if (ctrl->nand_version >= 0x0600)
504 ctrl->block_sizes = block_sizes_v6;
505 else
506 ctrl->block_sizes = block_sizes_v4;
507
508 if (ctrl->nand_version < 0x0400) {
509 ctrl->max_page_size = 4096;
510 ctrl->max_block_size = 512 * 1024;
511 }
512 }
513
514 /* Maximum spare area sector size (per 512B) */
515 if (ctrl->nand_version >= 0x0702)
516 ctrl->max_oob = 128;
517 else if (ctrl->nand_version >= 0x0600)
518 ctrl->max_oob = 64;
519 else if (ctrl->nand_version >= 0x0500)
520 ctrl->max_oob = 32;
521 else
522 ctrl->max_oob = 16;
523
524 /* v6.0 and newer (except v6.1) have prefetch support */
525 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
526 ctrl->features |= BRCMNAND_HAS_PREFETCH;
527
528 /*
529 * v6.x has cache mode, but it's implemented differently. Ignore it for
530 * now.
531 */
532 if (ctrl->nand_version >= 0x0700)
533 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
534
535 if (ctrl->nand_version >= 0x0500)
536 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
537
538 if (ctrl->nand_version >= 0x0700)
539 ctrl->features |= BRCMNAND_HAS_WP;
540 #ifndef __UBOOT__
541 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
542 #else
543 else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp"))
544 #endif /* __UBOOT__ */
545 ctrl->features |= BRCMNAND_HAS_WP;
546
547 return 0;
548 }
549
brcmnand_read_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg)550 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
551 enum brcmnand_reg reg)
552 {
553 u16 offs = ctrl->reg_offsets[reg];
554
555 if (offs)
556 return nand_readreg(ctrl, offs);
557 else
558 return 0;
559 }
560
brcmnand_write_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 val)561 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
562 enum brcmnand_reg reg, u32 val)
563 {
564 u16 offs = ctrl->reg_offsets[reg];
565
566 if (offs)
567 nand_writereg(ctrl, offs, val);
568 }
569
brcmnand_rmw_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 mask,unsigned int shift,u32 val)570 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
571 enum brcmnand_reg reg, u32 mask, unsigned
572 int shift, u32 val)
573 {
574 u32 tmp = brcmnand_read_reg(ctrl, reg);
575
576 tmp &= ~mask;
577 tmp |= val << shift;
578 brcmnand_write_reg(ctrl, reg, tmp);
579 }
580
brcmnand_read_fc(struct brcmnand_controller * ctrl,int word)581 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
582 {
583 return __raw_readl(ctrl->nand_fc + word * 4);
584 }
585
brcmnand_write_fc(struct brcmnand_controller * ctrl,int word,u32 val)586 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
587 int word, u32 val)
588 {
589 __raw_writel(val, ctrl->nand_fc + word * 4);
590 }
591
brcmnand_cs_offset(struct brcmnand_controller * ctrl,int cs,enum brcmnand_cs_reg reg)592 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
593 enum brcmnand_cs_reg reg)
594 {
595 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
596 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
597 u8 cs_offs;
598
599 if (cs == 0 && ctrl->cs0_offsets)
600 cs_offs = ctrl->cs0_offsets[reg];
601 else
602 cs_offs = ctrl->cs_offsets[reg];
603
604 if (cs && offs_cs1)
605 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
606
607 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
608 }
609
brcmnand_count_corrected(struct brcmnand_controller * ctrl)610 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
611 {
612 if (ctrl->nand_version < 0x0600)
613 return 1;
614 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
615 }
616
brcmnand_wr_corr_thresh(struct brcmnand_host * host,u8 val)617 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
618 {
619 struct brcmnand_controller *ctrl = host->ctrl;
620 unsigned int shift = 0, bits;
621 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
622 int cs = host->cs;
623
624 if (ctrl->nand_version >= 0x0702)
625 bits = 7;
626 else if (ctrl->nand_version >= 0x0600)
627 bits = 6;
628 else if (ctrl->nand_version >= 0x0500)
629 bits = 5;
630 else
631 bits = 4;
632
633 if (ctrl->nand_version >= 0x0702) {
634 if (cs >= 4)
635 reg = BRCMNAND_CORR_THRESHOLD_EXT;
636 shift = (cs % 4) * bits;
637 } else if (ctrl->nand_version >= 0x0600) {
638 if (cs >= 5)
639 reg = BRCMNAND_CORR_THRESHOLD_EXT;
640 shift = (cs % 5) * bits;
641 }
642 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
643 }
644
brcmnand_cmd_shift(struct brcmnand_controller * ctrl)645 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
646 {
647 if (ctrl->nand_version < 0x0602)
648 return 24;
649 return 0;
650 }
651
652 /***********************************************************************
653 * NAND ACC CONTROL bitfield
654 *
655 * Some bits have remained constant throughout hardware revision, while
656 * others have shifted around.
657 ***********************************************************************/
658
659 /* Constant for all versions (where supported) */
660 enum {
661 /* See BRCMNAND_HAS_CACHE_MODE */
662 ACC_CONTROL_CACHE_MODE = BIT(22),
663
664 /* See BRCMNAND_HAS_PREFETCH */
665 ACC_CONTROL_PREFETCH = BIT(23),
666
667 ACC_CONTROL_PAGE_HIT = BIT(24),
668 ACC_CONTROL_WR_PREEMPT = BIT(25),
669 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
670 ACC_CONTROL_RD_ERASED = BIT(27),
671 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
672 ACC_CONTROL_WR_ECC = BIT(30),
673 ACC_CONTROL_RD_ECC = BIT(31),
674 };
675
brcmnand_spare_area_mask(struct brcmnand_controller * ctrl)676 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
677 {
678 if (ctrl->nand_version >= 0x0702)
679 return GENMASK(7, 0);
680 else if (ctrl->nand_version >= 0x0600)
681 return GENMASK(6, 0);
682 else
683 return GENMASK(5, 0);
684 }
685
686 #define NAND_ACC_CONTROL_ECC_SHIFT 16
687 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
688
brcmnand_ecc_level_mask(struct brcmnand_controller * ctrl)689 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
690 {
691 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
692
693 mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
694
695 /* v7.2 includes additional ECC levels */
696 if (ctrl->nand_version >= 0x0702)
697 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
698
699 return mask;
700 }
701
brcmnand_set_ecc_enabled(struct brcmnand_host * host,int en)702 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
703 {
704 struct brcmnand_controller *ctrl = host->ctrl;
705 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
706 u32 acc_control = nand_readreg(ctrl, offs);
707 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
708
709 if (en) {
710 acc_control |= ecc_flags; /* enable RD/WR ECC */
711 acc_control |= host->hwcfg.ecc_level
712 << NAND_ACC_CONTROL_ECC_SHIFT;
713 } else {
714 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
715 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
716 }
717
718 nand_writereg(ctrl, offs, acc_control);
719 }
720
brcmnand_sector_1k_shift(struct brcmnand_controller * ctrl)721 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
722 {
723 if (ctrl->nand_version >= 0x0702)
724 return 9;
725 else if (ctrl->nand_version >= 0x0600)
726 return 7;
727 else if (ctrl->nand_version >= 0x0500)
728 return 6;
729 else
730 return -1;
731 }
732
brcmnand_get_sector_size_1k(struct brcmnand_host * host)733 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
734 {
735 struct brcmnand_controller *ctrl = host->ctrl;
736 int shift = brcmnand_sector_1k_shift(ctrl);
737 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
738 BRCMNAND_CS_ACC_CONTROL);
739
740 if (shift < 0)
741 return 0;
742
743 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
744 }
745
brcmnand_set_sector_size_1k(struct brcmnand_host * host,int val)746 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
747 {
748 struct brcmnand_controller *ctrl = host->ctrl;
749 int shift = brcmnand_sector_1k_shift(ctrl);
750 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
751 BRCMNAND_CS_ACC_CONTROL);
752 u32 tmp;
753
754 if (shift < 0)
755 return;
756
757 tmp = nand_readreg(ctrl, acc_control_offs);
758 tmp &= ~(1 << shift);
759 tmp |= (!!val) << shift;
760 nand_writereg(ctrl, acc_control_offs, tmp);
761 }
762
763 /***********************************************************************
764 * CS_NAND_SELECT
765 ***********************************************************************/
766
767 enum {
768 CS_SELECT_NAND_WP = BIT(29),
769 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
770 };
771
bcmnand_ctrl_poll_status(struct brcmnand_controller * ctrl,u32 mask,u32 expected_val,unsigned long timeout_ms)772 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
773 u32 mask, u32 expected_val,
774 unsigned long timeout_ms)
775 {
776 #ifndef __UBOOT__
777 unsigned long limit;
778 u32 val;
779
780 if (!timeout_ms)
781 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
782
783 limit = jiffies + msecs_to_jiffies(timeout_ms);
784 do {
785 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
786 if ((val & mask) == expected_val)
787 return 0;
788
789 cpu_relax();
790 } while (time_after(limit, jiffies));
791 #else
792 unsigned long base, limit;
793 u32 val;
794
795 if (!timeout_ms)
796 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
797
798 base = get_timer(0);
799 limit = CONFIG_SYS_HZ * timeout_ms / 1000;
800 do {
801 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
802 if ((val & mask) == expected_val)
803 return 0;
804
805 cpu_relax();
806 } while (get_timer(base) < limit);
807 #endif /* __UBOOT__ */
808
809 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
810 expected_val, val & mask);
811
812 return -ETIMEDOUT;
813 }
814
brcmnand_set_wp(struct brcmnand_controller * ctrl,bool en)815 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
816 {
817 u32 val = en ? CS_SELECT_NAND_WP : 0;
818
819 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
820 }
821
822 /***********************************************************************
823 * Flash DMA
824 ***********************************************************************/
825
826 enum flash_dma_reg {
827 FLASH_DMA_REVISION = 0x00,
828 FLASH_DMA_FIRST_DESC = 0x04,
829 FLASH_DMA_FIRST_DESC_EXT = 0x08,
830 FLASH_DMA_CTRL = 0x0c,
831 FLASH_DMA_MODE = 0x10,
832 FLASH_DMA_STATUS = 0x14,
833 FLASH_DMA_INTERRUPT_DESC = 0x18,
834 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
835 FLASH_DMA_ERROR_STATUS = 0x20,
836 FLASH_DMA_CURRENT_DESC = 0x24,
837 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
838 };
839
has_flash_dma(struct brcmnand_controller * ctrl)840 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
841 {
842 return ctrl->flash_dma_base;
843 }
844
flash_dma_buf_ok(const void * buf)845 static inline bool flash_dma_buf_ok(const void *buf)
846 {
847 #ifndef __UBOOT__
848 return buf && !is_vmalloc_addr(buf) &&
849 likely(IS_ALIGNED((uintptr_t)buf, 4));
850 #else
851 return buf && likely(IS_ALIGNED((uintptr_t)buf, 4));
852 #endif /* __UBOOT__ */
853 }
854
flash_dma_writel(struct brcmnand_controller * ctrl,u8 offs,u32 val)855 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
856 u32 val)
857 {
858 brcmnand_writel(val, ctrl->flash_dma_base + offs);
859 }
860
flash_dma_readl(struct brcmnand_controller * ctrl,u8 offs)861 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
862 {
863 return brcmnand_readl(ctrl->flash_dma_base + offs);
864 }
865
866 /* Low-level operation types: command, address, write, or read */
867 enum brcmnand_llop_type {
868 LL_OP_CMD,
869 LL_OP_ADDR,
870 LL_OP_WR,
871 LL_OP_RD,
872 };
873
874 /***********************************************************************
875 * Internal support functions
876 ***********************************************************************/
877
is_hamming_ecc(struct brcmnand_controller * ctrl,struct brcmnand_cfg * cfg)878 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
879 struct brcmnand_cfg *cfg)
880 {
881 if (ctrl->nand_version <= 0x0701)
882 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
883 cfg->ecc_level == 15;
884 else
885 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
886 cfg->ecc_level == 15) ||
887 (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
888 }
889
890 /*
891 * Returns a nand_ecclayout strucutre for the given layout/configuration.
892 * Returns NULL on failure.
893 */
brcmnand_create_layout(int ecc_level,struct brcmnand_host * host)894 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
895 struct brcmnand_host *host)
896 {
897 struct brcmnand_cfg *cfg = &host->hwcfg;
898 int i, j;
899 struct nand_ecclayout *layout;
900 int req;
901 int sectors;
902 int sas;
903 int idx1, idx2;
904
905 #ifndef __UBOOT__
906 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
907 #else
908 layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL);
909 #endif
910 if (!layout)
911 return NULL;
912
913 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
914 sas = cfg->spare_area_size << cfg->sector_size_1k;
915
916 /* Hamming */
917 if (is_hamming_ecc(host->ctrl, cfg)) {
918 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
919 /* First sector of each page may have BBI */
920 if (i == 0) {
921 layout->oobfree[idx2].offset = i * sas + 1;
922 /* Small-page NAND use byte 6 for BBI */
923 if (cfg->page_size == 512)
924 layout->oobfree[idx2].offset--;
925 layout->oobfree[idx2].length = 5;
926 } else {
927 layout->oobfree[idx2].offset = i * sas;
928 layout->oobfree[idx2].length = 6;
929 }
930 idx2++;
931 layout->eccpos[idx1++] = i * sas + 6;
932 layout->eccpos[idx1++] = i * sas + 7;
933 layout->eccpos[idx1++] = i * sas + 8;
934 layout->oobfree[idx2].offset = i * sas + 9;
935 layout->oobfree[idx2].length = 7;
936 idx2++;
937 /* Leave zero-terminated entry for OOBFREE */
938 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
939 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
940 break;
941 }
942
943 return layout;
944 }
945
946 /*
947 * CONTROLLER_VERSION:
948 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
949 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
950 * But we will just be conservative.
951 */
952 req = DIV_ROUND_UP(ecc_level * 14, 8);
953 if (req >= sas) {
954 dev_err(&host->pdev->dev,
955 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
956 req, sas);
957 return NULL;
958 }
959
960 layout->eccbytes = req * sectors;
961 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
962 for (j = sas - req; j < sas && idx1 <
963 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
964 layout->eccpos[idx1] = i * sas + j;
965
966 /* First sector of each page may have BBI */
967 if (i == 0) {
968 if (cfg->page_size == 512 && (sas - req >= 6)) {
969 /* Small-page NAND use byte 6 for BBI */
970 layout->oobfree[idx2].offset = 0;
971 layout->oobfree[idx2].length = 5;
972 idx2++;
973 if (sas - req > 6) {
974 layout->oobfree[idx2].offset = 6;
975 layout->oobfree[idx2].length =
976 sas - req - 6;
977 idx2++;
978 }
979 } else if (sas > req + 1) {
980 layout->oobfree[idx2].offset = i * sas + 1;
981 layout->oobfree[idx2].length = sas - req - 1;
982 idx2++;
983 }
984 } else if (sas > req) {
985 layout->oobfree[idx2].offset = i * sas;
986 layout->oobfree[idx2].length = sas - req;
987 idx2++;
988 }
989 /* Leave zero-terminated entry for OOBFREE */
990 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
991 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
992 break;
993 }
994
995 return layout;
996 }
997
brcmstb_choose_ecc_layout(struct brcmnand_host * host)998 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
999 struct brcmnand_host *host)
1000 {
1001 struct nand_ecclayout *layout;
1002 struct brcmnand_cfg *p = &host->hwcfg;
1003 unsigned int ecc_level = p->ecc_level;
1004
1005 if (p->sector_size_1k)
1006 ecc_level <<= 1;
1007
1008 layout = brcmnand_create_layout(ecc_level, host);
1009 if (!layout) {
1010 dev_err(&host->pdev->dev,
1011 "no proper ecc_layout for this NAND cfg\n");
1012 return NULL;
1013 }
1014
1015 return layout;
1016 }
1017
brcmnand_wp(struct mtd_info * mtd,int wp)1018 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1019 {
1020 struct nand_chip *chip = mtd_to_nand(mtd);
1021 struct brcmnand_host *host = nand_get_controller_data(chip);
1022 struct brcmnand_controller *ctrl = host->ctrl;
1023
1024 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1025 static int old_wp = -1;
1026 int ret;
1027
1028 if (old_wp != wp) {
1029 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1030 old_wp = wp;
1031 }
1032
1033 /*
1034 * make sure ctrl/flash ready before and after
1035 * changing state of #WP pin
1036 */
1037 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
1038 NAND_STATUS_READY,
1039 NAND_CTRL_RDY |
1040 NAND_STATUS_READY, 0);
1041 if (ret)
1042 return;
1043
1044 brcmnand_set_wp(ctrl, wp);
1045 nand_status_op(chip, NULL);
1046 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1047 ret = bcmnand_ctrl_poll_status(ctrl,
1048 NAND_CTRL_RDY |
1049 NAND_STATUS_READY |
1050 NAND_STATUS_WP,
1051 NAND_CTRL_RDY |
1052 NAND_STATUS_READY |
1053 (wp ? 0 : NAND_STATUS_WP), 0);
1054 #ifndef __UBOOT__
1055 if (ret)
1056 dev_err_ratelimited(&host->pdev->dev,
1057 "nand #WP expected %s\n",
1058 wp ? "on" : "off");
1059 #else
1060 if (ret)
1061 dev_err(&host->pdev->dev,
1062 "nand #WP expected %s\n",
1063 wp ? "on" : "off");
1064 #endif /* __UBOOT__ */
1065 }
1066 }
1067
1068 /* Helper functions for reading and writing OOB registers */
oob_reg_read(struct brcmnand_controller * ctrl,u32 offs)1069 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1070 {
1071 u16 offset0, offset10, reg_offs;
1072
1073 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1074 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1075
1076 if (offs >= ctrl->max_oob)
1077 return 0x77;
1078
1079 if (offs >= 16 && offset10)
1080 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1081 else
1082 reg_offs = offset0 + (offs & ~0x03);
1083
1084 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1085 }
1086
oob_reg_write(struct brcmnand_controller * ctrl,u32 offs,u32 data)1087 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1088 u32 data)
1089 {
1090 u16 offset0, offset10, reg_offs;
1091
1092 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1093 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1094
1095 if (offs >= ctrl->max_oob)
1096 return;
1097
1098 if (offs >= 16 && offset10)
1099 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1100 else
1101 reg_offs = offset0 + (offs & ~0x03);
1102
1103 nand_writereg(ctrl, reg_offs, data);
1104 }
1105
1106 /*
1107 * read_oob_from_regs - read data from OOB registers
1108 * @ctrl: NAND controller
1109 * @i: sub-page sector index
1110 * @oob: buffer to read to
1111 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1112 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1113 */
read_oob_from_regs(struct brcmnand_controller * ctrl,int i,u8 * oob,int sas,int sector_1k)1114 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1115 int sas, int sector_1k)
1116 {
1117 int tbytes = sas << sector_1k;
1118 int j;
1119
1120 /* Adjust OOB values for 1K sector size */
1121 if (sector_1k && (i & 0x01))
1122 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1123 tbytes = min_t(int, tbytes, ctrl->max_oob);
1124
1125 for (j = 0; j < tbytes; j++)
1126 oob[j] = oob_reg_read(ctrl, j);
1127 return tbytes;
1128 }
1129
1130 /*
1131 * write_oob_to_regs - write data to OOB registers
1132 * @i: sub-page sector index
1133 * @oob: buffer to write from
1134 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1135 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1136 */
write_oob_to_regs(struct brcmnand_controller * ctrl,int i,const u8 * oob,int sas,int sector_1k)1137 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1138 const u8 *oob, int sas, int sector_1k)
1139 {
1140 int tbytes = sas << sector_1k;
1141 int j;
1142
1143 /* Adjust OOB values for 1K sector size */
1144 if (sector_1k && (i & 0x01))
1145 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1146 tbytes = min_t(int, tbytes, ctrl->max_oob);
1147
1148 for (j = 0; j < tbytes; j += 4)
1149 oob_reg_write(ctrl, j,
1150 (oob[j + 0] << 24) |
1151 (oob[j + 1] << 16) |
1152 (oob[j + 2] << 8) |
1153 (oob[j + 3] << 0));
1154 return tbytes;
1155 }
1156
1157 #ifndef __UBOOT__
brcmnand_ctlrdy_irq(int irq,void * data)1158 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1159 {
1160 struct brcmnand_controller *ctrl = data;
1161
1162 /* Discard all NAND_CTLRDY interrupts during DMA */
1163 if (ctrl->dma_pending)
1164 return IRQ_HANDLED;
1165
1166 complete(&ctrl->done);
1167 return IRQ_HANDLED;
1168 }
1169
1170 /* Handle SoC-specific interrupt hardware */
brcmnand_irq(int irq,void * data)1171 static irqreturn_t brcmnand_irq(int irq, void *data)
1172 {
1173 struct brcmnand_controller *ctrl = data;
1174
1175 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1176 return brcmnand_ctlrdy_irq(irq, data);
1177
1178 return IRQ_NONE;
1179 }
1180
brcmnand_dma_irq(int irq,void * data)1181 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1182 {
1183 struct brcmnand_controller *ctrl = data;
1184
1185 complete(&ctrl->dma_done);
1186
1187 return IRQ_HANDLED;
1188 }
1189 #endif /* __UBOOT__ */
1190
brcmnand_send_cmd(struct brcmnand_host * host,int cmd)1191 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1192 {
1193 struct brcmnand_controller *ctrl = host->ctrl;
1194 int ret;
1195
1196 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1197 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1198 BUG_ON(ctrl->cmd_pending != 0);
1199 ctrl->cmd_pending = cmd;
1200
1201 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1202 WARN_ON(ret);
1203
1204 mb(); /* flush previous writes */
1205 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1206 cmd << brcmnand_cmd_shift(ctrl));
1207 }
1208
1209 /***********************************************************************
1210 * NAND MTD API: read/program/erase
1211 ***********************************************************************/
1212
brcmnand_cmd_ctrl(struct mtd_info * mtd,int dat,unsigned int ctrl)1213 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1214 unsigned int ctrl)
1215 {
1216 /* intentionally left blank */
1217 }
1218
brcmnand_waitfunc(struct mtd_info * mtd,struct nand_chip * this)1219 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1220 {
1221 struct nand_chip *chip = mtd_to_nand(mtd);
1222 struct brcmnand_host *host = nand_get_controller_data(chip);
1223 struct brcmnand_controller *ctrl = host->ctrl;
1224
1225 #ifndef __UBOOT__
1226 unsigned long timeo = msecs_to_jiffies(100);
1227
1228 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1229 if (ctrl->cmd_pending &&
1230 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1231 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1232 >> brcmnand_cmd_shift(ctrl);
1233
1234 dev_err_ratelimited(ctrl->dev,
1235 "timeout waiting for command %#02x\n", cmd);
1236 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1237 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1238 }
1239 #else
1240 unsigned long timeo = 100; /* 100 msec */
1241 int ret;
1242
1243 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1244
1245 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo);
1246 WARN_ON(ret);
1247 #endif /* __UBOOT__ */
1248
1249 ctrl->cmd_pending = 0;
1250 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1251 INTFC_FLASH_STATUS;
1252 }
1253
1254 enum {
1255 LLOP_RE = BIT(16),
1256 LLOP_WE = BIT(17),
1257 LLOP_ALE = BIT(18),
1258 LLOP_CLE = BIT(19),
1259 LLOP_RETURN_IDLE = BIT(31),
1260
1261 LLOP_DATA_MASK = GENMASK(15, 0),
1262 };
1263
brcmnand_low_level_op(struct brcmnand_host * host,enum brcmnand_llop_type type,u32 data,bool last_op)1264 static int brcmnand_low_level_op(struct brcmnand_host *host,
1265 enum brcmnand_llop_type type, u32 data,
1266 bool last_op)
1267 {
1268 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1269 struct nand_chip *chip = &host->chip;
1270 struct brcmnand_controller *ctrl = host->ctrl;
1271 u32 tmp;
1272
1273 tmp = data & LLOP_DATA_MASK;
1274 switch (type) {
1275 case LL_OP_CMD:
1276 tmp |= LLOP_WE | LLOP_CLE;
1277 break;
1278 case LL_OP_ADDR:
1279 /* WE | ALE */
1280 tmp |= LLOP_WE | LLOP_ALE;
1281 break;
1282 case LL_OP_WR:
1283 /* WE */
1284 tmp |= LLOP_WE;
1285 break;
1286 case LL_OP_RD:
1287 /* RE */
1288 tmp |= LLOP_RE;
1289 break;
1290 }
1291 if (last_op)
1292 /* RETURN_IDLE */
1293 tmp |= LLOP_RETURN_IDLE;
1294
1295 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1296
1297 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1298 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1299
1300 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1301 return brcmnand_waitfunc(mtd, chip);
1302 }
1303
brcmnand_cmdfunc(struct mtd_info * mtd,unsigned command,int column,int page_addr)1304 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1305 int column, int page_addr)
1306 {
1307 struct nand_chip *chip = mtd_to_nand(mtd);
1308 struct brcmnand_host *host = nand_get_controller_data(chip);
1309 struct brcmnand_controller *ctrl = host->ctrl;
1310 u64 addr = (u64)page_addr << chip->page_shift;
1311 int native_cmd = 0;
1312
1313 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1314 command == NAND_CMD_RNDOUT)
1315 addr = (u64)column;
1316 /* Avoid propagating a negative, don't-care address */
1317 else if (page_addr < 0)
1318 addr = 0;
1319
1320 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1321 (unsigned long long)addr);
1322
1323 host->last_cmd = command;
1324 host->last_byte = 0;
1325 host->last_addr = addr;
1326
1327 switch (command) {
1328 case NAND_CMD_RESET:
1329 native_cmd = CMD_FLASH_RESET;
1330 break;
1331 case NAND_CMD_STATUS:
1332 native_cmd = CMD_STATUS_READ;
1333 break;
1334 case NAND_CMD_READID:
1335 native_cmd = CMD_DEVICE_ID_READ;
1336 break;
1337 case NAND_CMD_READOOB:
1338 native_cmd = CMD_SPARE_AREA_READ;
1339 break;
1340 case NAND_CMD_ERASE1:
1341 native_cmd = CMD_BLOCK_ERASE;
1342 brcmnand_wp(mtd, 0);
1343 break;
1344 case NAND_CMD_PARAM:
1345 native_cmd = CMD_PARAMETER_READ;
1346 break;
1347 case NAND_CMD_SET_FEATURES:
1348 case NAND_CMD_GET_FEATURES:
1349 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1350 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1351 break;
1352 case NAND_CMD_RNDOUT:
1353 native_cmd = CMD_PARAMETER_CHANGE_COL;
1354 addr &= ~((u64)(FC_BYTES - 1));
1355 /*
1356 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1357 * NB: hwcfg.sector_size_1k may not be initialized yet
1358 */
1359 if (brcmnand_get_sector_size_1k(host)) {
1360 host->hwcfg.sector_size_1k =
1361 brcmnand_get_sector_size_1k(host);
1362 brcmnand_set_sector_size_1k(host, 0);
1363 }
1364 break;
1365 }
1366
1367 if (!native_cmd)
1368 return;
1369
1370 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1371 (host->cs << 16) | ((addr >> 32) & 0xffff));
1372 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1373 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1374 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1375
1376 brcmnand_send_cmd(host, native_cmd);
1377 brcmnand_waitfunc(mtd, chip);
1378
1379 if (native_cmd == CMD_PARAMETER_READ ||
1380 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1381 /* Copy flash cache word-wise */
1382 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1383 int i;
1384
1385 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1386
1387 /*
1388 * Must cache the FLASH_CACHE now, since changes in
1389 * SECTOR_SIZE_1K may invalidate it
1390 */
1391 for (i = 0; i < FC_WORDS; i++) {
1392 u32 fc;
1393
1394 fc = brcmnand_read_fc(ctrl, i);
1395
1396 /*
1397 * Flash cache is big endian for parameter pages, at
1398 * least on STB SoCs
1399 */
1400 if (ctrl->parameter_page_big_endian)
1401 flash_cache[i] = be32_to_cpu(fc);
1402 else
1403 flash_cache[i] = le32_to_cpu(fc);
1404 }
1405
1406 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1407
1408 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1409 if (host->hwcfg.sector_size_1k)
1410 brcmnand_set_sector_size_1k(host,
1411 host->hwcfg.sector_size_1k);
1412 }
1413
1414 /* Re-enable protection is necessary only after erase */
1415 if (command == NAND_CMD_ERASE1)
1416 brcmnand_wp(mtd, 1);
1417 }
1418
brcmnand_read_byte(struct mtd_info * mtd)1419 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1420 {
1421 struct nand_chip *chip = mtd_to_nand(mtd);
1422 struct brcmnand_host *host = nand_get_controller_data(chip);
1423 struct brcmnand_controller *ctrl = host->ctrl;
1424 uint8_t ret = 0;
1425 int addr, offs;
1426
1427 switch (host->last_cmd) {
1428 case NAND_CMD_READID:
1429 if (host->last_byte < 4)
1430 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1431 (24 - (host->last_byte << 3));
1432 else if (host->last_byte < 8)
1433 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1434 (56 - (host->last_byte << 3));
1435 break;
1436
1437 case NAND_CMD_READOOB:
1438 ret = oob_reg_read(ctrl, host->last_byte);
1439 break;
1440
1441 case NAND_CMD_STATUS:
1442 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1443 INTFC_FLASH_STATUS;
1444 if (wp_on) /* hide WP status */
1445 ret |= NAND_STATUS_WP;
1446 break;
1447
1448 case NAND_CMD_PARAM:
1449 case NAND_CMD_RNDOUT:
1450 addr = host->last_addr + host->last_byte;
1451 offs = addr & (FC_BYTES - 1);
1452
1453 /* At FC_BYTES boundary, switch to next column */
1454 if (host->last_byte > 0 && offs == 0)
1455 nand_change_read_column_op(chip, addr, NULL, 0, false);
1456
1457 ret = ctrl->flash_cache[offs];
1458 break;
1459 case NAND_CMD_GET_FEATURES:
1460 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1461 ret = 0;
1462 } else {
1463 bool last = host->last_byte ==
1464 ONFI_SUBFEATURE_PARAM_LEN - 1;
1465 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1466 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1467 }
1468 }
1469
1470 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1471 host->last_byte++;
1472
1473 return ret;
1474 }
1475
brcmnand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)1476 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1477 {
1478 int i;
1479
1480 for (i = 0; i < len; i++, buf++)
1481 *buf = brcmnand_read_byte(mtd);
1482 }
1483
brcmnand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)1484 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1485 int len)
1486 {
1487 int i;
1488 struct nand_chip *chip = mtd_to_nand(mtd);
1489 struct brcmnand_host *host = nand_get_controller_data(chip);
1490
1491 switch (host->last_cmd) {
1492 case NAND_CMD_SET_FEATURES:
1493 for (i = 0; i < len; i++)
1494 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1495 (i + 1) == len);
1496 break;
1497 default:
1498 BUG();
1499 break;
1500 }
1501 }
1502
1503 /**
1504 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1505 * following ahead of time:
1506 * - Is this descriptor the beginning or end of a linked list?
1507 * - What is the (DMA) address of the next descriptor in the linked list?
1508 */
1509 #ifndef __UBOOT__
brcmnand_fill_dma_desc(struct brcmnand_host * host,struct brcm_nand_dma_desc * desc,u64 addr,dma_addr_t buf,u32 len,u8 dma_cmd,bool begin,bool end,dma_addr_t next_desc)1510 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1511 struct brcm_nand_dma_desc *desc, u64 addr,
1512 dma_addr_t buf, u32 len, u8 dma_cmd,
1513 bool begin, bool end,
1514 dma_addr_t next_desc)
1515 {
1516 memset(desc, 0, sizeof(*desc));
1517 /* Descriptors are written in native byte order (wordwise) */
1518 desc->next_desc = lower_32_bits(next_desc);
1519 desc->next_desc_ext = upper_32_bits(next_desc);
1520 desc->cmd_irq = (dma_cmd << 24) |
1521 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1522 (!!begin) | ((!!end) << 1); /* head, tail */
1523 #ifdef CONFIG_CPU_BIG_ENDIAN
1524 desc->cmd_irq |= 0x01 << 12;
1525 #endif
1526 desc->dram_addr = lower_32_bits(buf);
1527 desc->dram_addr_ext = upper_32_bits(buf);
1528 desc->tfr_len = len;
1529 desc->total_len = len;
1530 desc->flash_addr = lower_32_bits(addr);
1531 desc->flash_addr_ext = upper_32_bits(addr);
1532 desc->cs = host->cs;
1533 desc->status_valid = 0x01;
1534 return 0;
1535 }
1536
1537 /**
1538 * Kick the FLASH_DMA engine, with a given DMA descriptor
1539 */
brcmnand_dma_run(struct brcmnand_host * host,dma_addr_t desc)1540 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1541 {
1542 struct brcmnand_controller *ctrl = host->ctrl;
1543 unsigned long timeo = msecs_to_jiffies(100);
1544
1545 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1546 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1547 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1548 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1549
1550 /* Start FLASH_DMA engine */
1551 ctrl->dma_pending = true;
1552 mb(); /* flush previous writes */
1553 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1554
1555 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1556 dev_err(ctrl->dev,
1557 "timeout waiting for DMA; status %#x, error status %#x\n",
1558 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1559 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1560 }
1561 ctrl->dma_pending = false;
1562 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1563 }
1564
brcmnand_dma_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u32 len,u8 dma_cmd)1565 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1566 u32 len, u8 dma_cmd)
1567 {
1568 struct brcmnand_controller *ctrl = host->ctrl;
1569 dma_addr_t buf_pa;
1570 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1571
1572 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1573 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1574 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1575 return -ENOMEM;
1576 }
1577
1578 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1579 dma_cmd, true, true, 0);
1580
1581 brcmnand_dma_run(host, ctrl->dma_pa);
1582
1583 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1584
1585 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1586 return -EBADMSG;
1587 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1588 return -EUCLEAN;
1589
1590 return 0;
1591 }
1592 #endif /* __UBOOT__ */
1593
1594 /*
1595 * Assumes proper CS is already set
1596 */
brcmnand_read_by_pio(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob,u64 * err_addr)1597 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1598 u64 addr, unsigned int trans, u32 *buf,
1599 u8 *oob, u64 *err_addr)
1600 {
1601 struct brcmnand_host *host = nand_get_controller_data(chip);
1602 struct brcmnand_controller *ctrl = host->ctrl;
1603 int i, j, ret = 0;
1604
1605 /* Clear error addresses */
1606 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1607 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1608 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1609 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1610
1611 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1612 (host->cs << 16) | ((addr >> 32) & 0xffff));
1613 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1614
1615 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1616 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1617 lower_32_bits(addr));
1618 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1619 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1620 brcmnand_send_cmd(host, CMD_PAGE_READ);
1621 brcmnand_waitfunc(mtd, chip);
1622
1623 if (likely(buf)) {
1624 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1625
1626 for (j = 0; j < FC_WORDS; j++, buf++)
1627 *buf = brcmnand_read_fc(ctrl, j);
1628
1629 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1630 }
1631
1632 if (oob)
1633 oob += read_oob_from_regs(ctrl, i, oob,
1634 mtd->oobsize / trans,
1635 host->hwcfg.sector_size_1k);
1636
1637 if (!ret) {
1638 *err_addr = brcmnand_read_reg(ctrl,
1639 BRCMNAND_UNCORR_ADDR) |
1640 ((u64)(brcmnand_read_reg(ctrl,
1641 BRCMNAND_UNCORR_EXT_ADDR)
1642 & 0xffff) << 32);
1643 if (*err_addr)
1644 ret = -EBADMSG;
1645 }
1646
1647 if (!ret) {
1648 *err_addr = brcmnand_read_reg(ctrl,
1649 BRCMNAND_CORR_ADDR) |
1650 ((u64)(brcmnand_read_reg(ctrl,
1651 BRCMNAND_CORR_EXT_ADDR)
1652 & 0xffff) << 32);
1653 if (*err_addr)
1654 ret = -EUCLEAN;
1655 }
1656 }
1657
1658 return ret;
1659 }
1660
1661 /*
1662 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1663 * error
1664 *
1665 * Because the HW ECC signals an ECC error if an erase paged has even a single
1666 * bitflip, we must check each ECC error to see if it is actually an erased
1667 * page with bitflips, not a truly corrupted page.
1668 *
1669 * On a real error, return a negative error code (-EBADMSG for ECC error), and
1670 * buf will contain raw data.
1671 * Otherwise, buf gets filled with 0xffs and return the maximum number of
1672 * bitflips-per-ECC-sector to the caller.
1673 *
1674 */
brcmstb_nand_verify_erased_page(struct mtd_info * mtd,struct nand_chip * chip,void * buf,u64 addr)1675 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1676 struct nand_chip *chip, void *buf, u64 addr)
1677 {
1678 int i, sas;
1679 void *oob = chip->oob_poi;
1680 int bitflips = 0;
1681 int page = addr >> chip->page_shift;
1682 int ret;
1683
1684 if (!buf) {
1685 #ifndef __UBOOT__
1686 buf = chip->data_buf;
1687 #else
1688 buf = chip->buffers->databuf;
1689 #endif
1690 /* Invalidate page cache */
1691 chip->pagebuf = -1;
1692 }
1693
1694 sas = mtd->oobsize / chip->ecc.steps;
1695
1696 /* read without ecc for verification */
1697 ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1698 if (ret)
1699 return ret;
1700
1701 for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1702 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1703 oob, sas, NULL, 0,
1704 chip->ecc.strength);
1705 if (ret < 0)
1706 return ret;
1707
1708 bitflips = max(bitflips, ret);
1709 }
1710
1711 return bitflips;
1712 }
1713
brcmnand_read(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob)1714 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1715 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1716 {
1717 struct brcmnand_host *host = nand_get_controller_data(chip);
1718 struct brcmnand_controller *ctrl = host->ctrl;
1719 u64 err_addr = 0;
1720 int err;
1721 bool retry = true;
1722
1723 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1724
1725 try_dmaread:
1726 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1727
1728 #ifndef __UBOOT__
1729 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1730 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1731 CMD_PAGE_READ);
1732 if (err) {
1733 if (mtd_is_bitflip_or_eccerr(err))
1734 err_addr = addr;
1735 else
1736 return -EIO;
1737 }
1738 } else {
1739 if (oob)
1740 memset(oob, 0x99, mtd->oobsize);
1741
1742 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1743 oob, &err_addr);
1744 }
1745 #else
1746 if (oob)
1747 memset(oob, 0x99, mtd->oobsize);
1748
1749 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1750 oob, &err_addr);
1751 #endif /* __UBOOT__ */
1752
1753 if (mtd_is_eccerr(err)) {
1754 /*
1755 * On controller version and 7.0, 7.1 , DMA read after a
1756 * prior PIO read that reported uncorrectable error,
1757 * the DMA engine captures this error following DMA read
1758 * cleared only on subsequent DMA read, so just retry once
1759 * to clear a possible false error reported for current DMA
1760 * read
1761 */
1762 if ((ctrl->nand_version == 0x0700) ||
1763 (ctrl->nand_version == 0x0701)) {
1764 if (retry) {
1765 retry = false;
1766 goto try_dmaread;
1767 }
1768 }
1769
1770 /*
1771 * Controller version 7.2 has hw encoder to detect erased page
1772 * bitflips, apply sw verification for older controllers only
1773 */
1774 if (ctrl->nand_version < 0x0702) {
1775 err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1776 addr);
1777 /* erased page bitflips corrected */
1778 if (err >= 0)
1779 return err;
1780 }
1781
1782 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1783 (unsigned long long)err_addr);
1784 mtd->ecc_stats.failed++;
1785 /* NAND layer expects zero on ECC errors */
1786 return 0;
1787 }
1788
1789 if (mtd_is_bitflip(err)) {
1790 unsigned int corrected = brcmnand_count_corrected(ctrl);
1791
1792 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1793 (unsigned long long)err_addr);
1794 mtd->ecc_stats.corrected += corrected;
1795 /* Always exceed the software-imposed threshold */
1796 return max(mtd->bitflip_threshold, corrected);
1797 }
1798
1799 return 0;
1800 }
1801
brcmnand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1802 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1803 uint8_t *buf, int oob_required, int page)
1804 {
1805 struct brcmnand_host *host = nand_get_controller_data(chip);
1806 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1807
1808 nand_read_page_op(chip, page, 0, NULL, 0);
1809
1810 return brcmnand_read(mtd, chip, host->last_addr,
1811 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1812 }
1813
brcmnand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1814 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1815 uint8_t *buf, int oob_required, int page)
1816 {
1817 struct brcmnand_host *host = nand_get_controller_data(chip);
1818 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1819 int ret;
1820
1821 nand_read_page_op(chip, page, 0, NULL, 0);
1822
1823 brcmnand_set_ecc_enabled(host, 0);
1824 ret = brcmnand_read(mtd, chip, host->last_addr,
1825 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1826 brcmnand_set_ecc_enabled(host, 1);
1827 return ret;
1828 }
1829
brcmnand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1830 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1831 int page)
1832 {
1833 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1834 mtd->writesize >> FC_SHIFT,
1835 NULL, (u8 *)chip->oob_poi);
1836 }
1837
brcmnand_read_oob_raw(struct mtd_info * mtd,struct nand_chip * chip,int page)1838 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1839 int page)
1840 {
1841 struct brcmnand_host *host = nand_get_controller_data(chip);
1842
1843 brcmnand_set_ecc_enabled(host, 0);
1844 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1845 mtd->writesize >> FC_SHIFT,
1846 NULL, (u8 *)chip->oob_poi);
1847 brcmnand_set_ecc_enabled(host, 1);
1848 return 0;
1849 }
1850
brcmnand_write(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,const u32 * buf,u8 * oob)1851 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1852 u64 addr, const u32 *buf, u8 *oob)
1853 {
1854 struct brcmnand_host *host = nand_get_controller_data(chip);
1855 struct brcmnand_controller *ctrl = host->ctrl;
1856 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1857 int status, ret = 0;
1858
1859 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1860
1861 if (unlikely((unsigned long)buf & 0x03)) {
1862 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1863 buf = (u32 *)((unsigned long)buf & ~0x03);
1864 }
1865
1866 brcmnand_wp(mtd, 0);
1867
1868 for (i = 0; i < ctrl->max_oob; i += 4)
1869 oob_reg_write(ctrl, i, 0xffffffff);
1870
1871 #ifndef __UBOOT__
1872 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1873 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1874 mtd->writesize, CMD_PROGRAM_PAGE))
1875 ret = -EIO;
1876 goto out;
1877 }
1878 #endif /* __UBOOT__ */
1879
1880 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1881 (host->cs << 16) | ((addr >> 32) & 0xffff));
1882 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1883
1884 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1885 /* full address MUST be set before populating FC */
1886 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1887 lower_32_bits(addr));
1888 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1889
1890 if (buf) {
1891 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1892
1893 for (j = 0; j < FC_WORDS; j++, buf++)
1894 brcmnand_write_fc(ctrl, j, *buf);
1895
1896 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1897 } else if (oob) {
1898 for (j = 0; j < FC_WORDS; j++)
1899 brcmnand_write_fc(ctrl, j, 0xffffffff);
1900 }
1901
1902 if (oob) {
1903 oob += write_oob_to_regs(ctrl, i, oob,
1904 mtd->oobsize / trans,
1905 host->hwcfg.sector_size_1k);
1906 }
1907
1908 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1909 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1910 status = brcmnand_waitfunc(mtd, chip);
1911
1912 if (status & NAND_STATUS_FAIL) {
1913 dev_info(ctrl->dev, "program failed at %llx\n",
1914 (unsigned long long)addr);
1915 ret = -EIO;
1916 goto out;
1917 }
1918 }
1919 out:
1920 brcmnand_wp(mtd, 1);
1921 return ret;
1922 }
1923
brcmnand_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1924 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1925 const uint8_t *buf, int oob_required, int page)
1926 {
1927 struct brcmnand_host *host = nand_get_controller_data(chip);
1928 void *oob = oob_required ? chip->oob_poi : NULL;
1929
1930 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1931 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1932
1933 return nand_prog_page_end_op(chip);
1934 }
1935
brcmnand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1936 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1937 struct nand_chip *chip, const uint8_t *buf,
1938 int oob_required, int page)
1939 {
1940 struct brcmnand_host *host = nand_get_controller_data(chip);
1941 void *oob = oob_required ? chip->oob_poi : NULL;
1942
1943 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1944 brcmnand_set_ecc_enabled(host, 0);
1945 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1946 brcmnand_set_ecc_enabled(host, 1);
1947
1948 return nand_prog_page_end_op(chip);
1949 }
1950
brcmnand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1951 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1952 int page)
1953 {
1954 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1955 NULL, chip->oob_poi);
1956 }
1957
brcmnand_write_oob_raw(struct mtd_info * mtd,struct nand_chip * chip,int page)1958 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1959 int page)
1960 {
1961 struct brcmnand_host *host = nand_get_controller_data(chip);
1962 int ret;
1963
1964 brcmnand_set_ecc_enabled(host, 0);
1965 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1966 (u8 *)chip->oob_poi);
1967 brcmnand_set_ecc_enabled(host, 1);
1968
1969 return ret;
1970 }
1971
1972 /***********************************************************************
1973 * Per-CS setup (1 NAND device)
1974 ***********************************************************************/
1975
brcmnand_set_cfg(struct brcmnand_host * host,struct brcmnand_cfg * cfg)1976 static int brcmnand_set_cfg(struct brcmnand_host *host,
1977 struct brcmnand_cfg *cfg)
1978 {
1979 struct brcmnand_controller *ctrl = host->ctrl;
1980 struct nand_chip *chip = &host->chip;
1981 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1982 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1983 BRCMNAND_CS_CFG_EXT);
1984 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1985 BRCMNAND_CS_ACC_CONTROL);
1986 u8 block_size = 0, page_size = 0, device_size = 0;
1987 u32 tmp;
1988
1989 if (ctrl->block_sizes) {
1990 int i, found;
1991
1992 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1993 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1994 block_size = i;
1995 found = 1;
1996 }
1997 if (!found) {
1998 dev_warn(ctrl->dev, "invalid block size %u\n",
1999 cfg->block_size);
2000 return -EINVAL;
2001 }
2002 } else {
2003 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
2004 }
2005
2006 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
2007 cfg->block_size > ctrl->max_block_size)) {
2008 dev_warn(ctrl->dev, "invalid block size %u\n",
2009 cfg->block_size);
2010 block_size = 0;
2011 }
2012
2013 if (ctrl->page_sizes) {
2014 int i, found;
2015
2016 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2017 if (ctrl->page_sizes[i] == cfg->page_size) {
2018 page_size = i;
2019 found = 1;
2020 }
2021 if (!found) {
2022 dev_warn(ctrl->dev, "invalid page size %u\n",
2023 cfg->page_size);
2024 return -EINVAL;
2025 }
2026 } else {
2027 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2028 }
2029
2030 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2031 cfg->page_size > ctrl->max_page_size)) {
2032 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2033 return -EINVAL;
2034 }
2035
2036 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2037 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2038 (unsigned long long)cfg->device_size);
2039 return -EINVAL;
2040 }
2041 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2042
2043 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2044 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2045 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2046 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2047 (device_size << CFG_DEVICE_SIZE_SHIFT);
2048 if (cfg_offs == cfg_ext_offs) {
2049 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
2050 (block_size << CFG_BLK_SIZE_SHIFT);
2051 nand_writereg(ctrl, cfg_offs, tmp);
2052 } else {
2053 nand_writereg(ctrl, cfg_offs, tmp);
2054 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2055 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2056 nand_writereg(ctrl, cfg_ext_offs, tmp);
2057 }
2058
2059 tmp = nand_readreg(ctrl, acc_control_offs);
2060 tmp &= ~brcmnand_ecc_level_mask(ctrl);
2061 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2062 tmp &= ~brcmnand_spare_area_mask(ctrl);
2063 tmp |= cfg->spare_area_size;
2064 nand_writereg(ctrl, acc_control_offs, tmp);
2065
2066 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2067
2068 /* threshold = ceil(BCH-level * 0.75) */
2069 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2070
2071 return 0;
2072 }
2073
brcmnand_print_cfg(struct brcmnand_host * host,char * buf,struct brcmnand_cfg * cfg)2074 static void brcmnand_print_cfg(struct brcmnand_host *host,
2075 char *buf, struct brcmnand_cfg *cfg)
2076 {
2077 buf += sprintf(buf,
2078 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2079 (unsigned long long)cfg->device_size >> 20,
2080 cfg->block_size >> 10,
2081 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2082 cfg->page_size >= 1024 ? "KiB" : "B",
2083 cfg->spare_area_size, cfg->device_width);
2084
2085 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2086 if (is_hamming_ecc(host->ctrl, cfg))
2087 sprintf(buf, ", Hamming ECC");
2088 else if (cfg->sector_size_1k)
2089 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2090 else
2091 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2092 }
2093
2094 /*
2095 * Minimum number of bytes to address a page. Calculated as:
2096 * roundup(log2(size / page-size) / 8)
2097 *
2098 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2099 * OK because many other things will break if 'size' is irregular...
2100 */
get_blk_adr_bytes(u64 size,u32 writesize)2101 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2102 {
2103 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2104 }
2105
brcmnand_setup_dev(struct brcmnand_host * host)2106 static int brcmnand_setup_dev(struct brcmnand_host *host)
2107 {
2108 struct mtd_info *mtd = nand_to_mtd(&host->chip);
2109 struct nand_chip *chip = &host->chip;
2110 struct brcmnand_controller *ctrl = host->ctrl;
2111 struct brcmnand_cfg *cfg = &host->hwcfg;
2112 char msg[128];
2113 u32 offs, tmp, oob_sector;
2114 int ret;
2115
2116 memset(cfg, 0, sizeof(*cfg));
2117
2118 #ifndef __UBOOT__
2119 ret = of_property_read_u32(nand_get_flash_node(chip),
2120 "brcm,nand-oob-sector-size",
2121 &oob_sector);
2122 #else
2123 ret = ofnode_read_u32(nand_get_flash_node(chip),
2124 "brcm,nand-oob-sector-size",
2125 &oob_sector);
2126 #endif /* __UBOOT__ */
2127 if (ret) {
2128 /* Use detected size */
2129 cfg->spare_area_size = mtd->oobsize /
2130 (mtd->writesize >> FC_SHIFT);
2131 } else {
2132 cfg->spare_area_size = oob_sector;
2133 }
2134 if (cfg->spare_area_size > ctrl->max_oob)
2135 cfg->spare_area_size = ctrl->max_oob;
2136 /*
2137 * Set oobsize to be consistent with controller's spare_area_size, as
2138 * the rest is inaccessible.
2139 */
2140 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2141
2142 cfg->device_size = mtd->size;
2143 cfg->block_size = mtd->erasesize;
2144 cfg->page_size = mtd->writesize;
2145 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2146 cfg->col_adr_bytes = 2;
2147 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2148
2149 if (chip->ecc.mode != NAND_ECC_HW) {
2150 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2151 chip->ecc.mode);
2152 return -EINVAL;
2153 }
2154
2155 if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2156 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2157 /* Default to Hamming for 1-bit ECC, if unspecified */
2158 chip->ecc.algo = NAND_ECC_HAMMING;
2159 else
2160 /* Otherwise, BCH */
2161 chip->ecc.algo = NAND_ECC_BCH;
2162 }
2163
2164 if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2165 chip->ecc.size != 512)) {
2166 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2167 chip->ecc.strength, chip->ecc.size);
2168 return -EINVAL;
2169 }
2170
2171 switch (chip->ecc.size) {
2172 case 512:
2173 if (chip->ecc.algo == NAND_ECC_HAMMING)
2174 cfg->ecc_level = 15;
2175 else
2176 cfg->ecc_level = chip->ecc.strength;
2177 cfg->sector_size_1k = 0;
2178 break;
2179 case 1024:
2180 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2181 dev_err(ctrl->dev, "1KB sectors not supported\n");
2182 return -EINVAL;
2183 }
2184 if (chip->ecc.strength & 0x1) {
2185 dev_err(ctrl->dev,
2186 "odd ECC not supported with 1KB sectors\n");
2187 return -EINVAL;
2188 }
2189
2190 cfg->ecc_level = chip->ecc.strength >> 1;
2191 cfg->sector_size_1k = 1;
2192 break;
2193 default:
2194 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2195 chip->ecc.size);
2196 return -EINVAL;
2197 }
2198
2199 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2200 if (mtd->writesize > 512)
2201 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2202 else
2203 cfg->ful_adr_bytes += 1;
2204
2205 ret = brcmnand_set_cfg(host, cfg);
2206 if (ret)
2207 return ret;
2208
2209 brcmnand_set_ecc_enabled(host, 1);
2210
2211 brcmnand_print_cfg(host, msg, cfg);
2212 dev_info(ctrl->dev, "detected %s\n", msg);
2213
2214 /* Configure ACC_CONTROL */
2215 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2216 tmp = nand_readreg(ctrl, offs);
2217 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2218 tmp &= ~ACC_CONTROL_RD_ERASED;
2219
2220 /* We need to turn on Read from erased paged protected by ECC */
2221 if (ctrl->nand_version >= 0x0702)
2222 tmp |= ACC_CONTROL_RD_ERASED;
2223 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2224 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2225 tmp &= ~ACC_CONTROL_PREFETCH;
2226
2227 nand_writereg(ctrl, offs, tmp);
2228
2229 return 0;
2230 }
2231
2232 #ifndef __UBOOT__
brcmnand_init_cs(struct brcmnand_host * host,struct device_node * dn)2233 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2234 #else
2235 static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
2236 #endif
2237 {
2238 struct brcmnand_controller *ctrl = host->ctrl;
2239 #ifndef __UBOOT__
2240 struct platform_device *pdev = host->pdev;
2241 #else
2242 struct udevice *pdev = host->pdev;
2243 #endif /* __UBOOT__ */
2244 struct mtd_info *mtd;
2245 struct nand_chip *chip;
2246 int ret;
2247 u16 cfg_offs;
2248
2249 #ifndef __UBOOT__
2250 ret = of_property_read_u32(dn, "reg", &host->cs);
2251 #else
2252 ret = ofnode_read_s32(dn, "reg", &host->cs);
2253 #endif
2254 if (ret) {
2255 dev_err(&pdev->dev, "can't get chip-select\n");
2256 return -ENXIO;
2257 }
2258
2259 mtd = nand_to_mtd(&host->chip);
2260 chip = &host->chip;
2261
2262 nand_set_flash_node(chip, dn);
2263 nand_set_controller_data(chip, host);
2264 #ifndef __UBOOT__
2265 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2266 host->cs);
2267 #else
2268 mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d",
2269 host->cs);
2270 #endif /* __UBOOT__ */
2271 if (!mtd->name)
2272 return -ENOMEM;
2273
2274 mtd->owner = THIS_MODULE;
2275 #ifndef __UBOOT__
2276 mtd->dev.parent = &pdev->dev;
2277 #else
2278 mtd->dev->parent = pdev;
2279 #endif /* __UBOOT__ */
2280
2281 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2282 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2283
2284 chip->cmd_ctrl = brcmnand_cmd_ctrl;
2285 chip->cmdfunc = brcmnand_cmdfunc;
2286 chip->waitfunc = brcmnand_waitfunc;
2287 chip->read_byte = brcmnand_read_byte;
2288 chip->read_buf = brcmnand_read_buf;
2289 chip->write_buf = brcmnand_write_buf;
2290
2291 chip->ecc.mode = NAND_ECC_HW;
2292 chip->ecc.read_page = brcmnand_read_page;
2293 chip->ecc.write_page = brcmnand_write_page;
2294 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2295 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2296 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2297 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2298 chip->ecc.read_oob = brcmnand_read_oob;
2299 chip->ecc.write_oob = brcmnand_write_oob;
2300
2301 chip->controller = &ctrl->controller;
2302
2303 /*
2304 * The bootloader might have configured 16bit mode but
2305 * NAND READID command only works in 8bit mode. We force
2306 * 8bit mode here to ensure that NAND READID commands works.
2307 */
2308 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2309 nand_writereg(ctrl, cfg_offs,
2310 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2311
2312 ret = nand_scan_ident(mtd, 1, NULL);
2313 if (ret)
2314 return ret;
2315
2316 chip->options |= NAND_NO_SUBPAGE_WRITE;
2317 /*
2318 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2319 * to/from, and have nand_base pass us a bounce buffer instead, as
2320 * needed.
2321 */
2322 chip->options |= NAND_USE_BOUNCE_BUFFER;
2323
2324 if (chip->bbt_options & NAND_BBT_USE_FLASH)
2325 chip->bbt_options |= NAND_BBT_NO_OOB;
2326
2327 if (brcmnand_setup_dev(host))
2328 return -ENXIO;
2329
2330 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2331 /* only use our internal HW threshold */
2332 mtd->bitflip_threshold = 1;
2333
2334 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2335 if (!chip->ecc.layout)
2336 return -ENXIO;
2337
2338 ret = nand_scan_tail(mtd);
2339 if (ret)
2340 return ret;
2341
2342 #ifndef __UBOOT__
2343 ret = mtd_device_register(mtd, NULL, 0);
2344 if (ret)
2345 nand_cleanup(chip);
2346 #else
2347 ret = nand_register(0, mtd);
2348 #endif /* __UBOOT__ */
2349
2350 return ret;
2351 }
2352
2353 #ifndef __UBOOT__
brcmnand_save_restore_cs_config(struct brcmnand_host * host,int restore)2354 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2355 int restore)
2356 {
2357 struct brcmnand_controller *ctrl = host->ctrl;
2358 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2359 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2360 BRCMNAND_CS_CFG_EXT);
2361 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2362 BRCMNAND_CS_ACC_CONTROL);
2363 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2364 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2365
2366 if (restore) {
2367 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2368 if (cfg_offs != cfg_ext_offs)
2369 nand_writereg(ctrl, cfg_ext_offs,
2370 host->hwcfg.config_ext);
2371 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2372 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2373 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2374 } else {
2375 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2376 if (cfg_offs != cfg_ext_offs)
2377 host->hwcfg.config_ext =
2378 nand_readreg(ctrl, cfg_ext_offs);
2379 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2380 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2381 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2382 }
2383 }
2384
brcmnand_suspend(struct device * dev)2385 static int brcmnand_suspend(struct device *dev)
2386 {
2387 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2388 struct brcmnand_host *host;
2389
2390 list_for_each_entry(host, &ctrl->host_list, node)
2391 brcmnand_save_restore_cs_config(host, 0);
2392
2393 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2394 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2395 ctrl->corr_stat_threshold =
2396 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2397
2398 if (has_flash_dma(ctrl))
2399 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2400
2401 return 0;
2402 }
2403
brcmnand_resume(struct device * dev)2404 static int brcmnand_resume(struct device *dev)
2405 {
2406 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2407 struct brcmnand_host *host;
2408
2409 if (has_flash_dma(ctrl)) {
2410 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2411 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2412 }
2413
2414 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2415 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2416 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2417 ctrl->corr_stat_threshold);
2418 if (ctrl->soc) {
2419 /* Clear/re-enable interrupt */
2420 ctrl->soc->ctlrdy_ack(ctrl->soc);
2421 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2422 }
2423
2424 list_for_each_entry(host, &ctrl->host_list, node) {
2425 struct nand_chip *chip = &host->chip;
2426
2427 brcmnand_save_restore_cs_config(host, 1);
2428
2429 /* Reset the chip, required by some chips after power-up */
2430 nand_reset_op(chip);
2431 }
2432
2433 return 0;
2434 }
2435
2436 const struct dev_pm_ops brcmnand_pm_ops = {
2437 .suspend = brcmnand_suspend,
2438 .resume = brcmnand_resume,
2439 };
2440 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2441
2442 static const struct of_device_id brcmnand_of_match[] = {
2443 { .compatible = "brcm,brcmnand-v4.0" },
2444 { .compatible = "brcm,brcmnand-v5.0" },
2445 { .compatible = "brcm,brcmnand-v6.0" },
2446 { .compatible = "brcm,brcmnand-v6.1" },
2447 { .compatible = "brcm,brcmnand-v6.2" },
2448 { .compatible = "brcm,brcmnand-v7.0" },
2449 { .compatible = "brcm,brcmnand-v7.1" },
2450 { .compatible = "brcm,brcmnand-v7.2" },
2451 {},
2452 };
2453 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2454 #endif /* __UBOOT__ */
2455
2456 /***********************************************************************
2457 * Platform driver setup (per controller)
2458 ***********************************************************************/
2459
2460 #ifndef __UBOOT__
brcmnand_probe(struct platform_device * pdev,struct brcmnand_soc * soc)2461 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2462 #else
2463 int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
2464 #endif /* __UBOOT__ */
2465 {
2466 #ifndef __UBOOT__
2467 struct device *dev = &pdev->dev;
2468 struct device_node *dn = dev->of_node, *child;
2469 #else
2470 ofnode child;
2471 struct udevice *pdev = dev;
2472 #endif /* __UBOOT__ */
2473 struct brcmnand_controller *ctrl;
2474 #ifndef __UBOOT__
2475 struct resource *res;
2476 #else
2477 struct resource res;
2478 #endif /* __UBOOT__ */
2479 int ret;
2480
2481 #ifndef __UBOOT__
2482 /* We only support device-tree instantiation */
2483 if (!dn)
2484 return -ENODEV;
2485
2486 if (!of_match_node(brcmnand_of_match, dn))
2487 return -ENODEV;
2488 #endif /* __UBOOT__ */
2489
2490 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2491 if (!ctrl)
2492 return -ENOMEM;
2493
2494 #ifndef __UBOOT__
2495 dev_set_drvdata(dev, ctrl);
2496 #else
2497 /*
2498 * in u-boot, the data for the driver is allocated before probing
2499 * so to keep the reference to ctrl, we store it in the variable soc
2500 */
2501 soc->ctrl = ctrl;
2502 #endif /* __UBOOT__ */
2503 ctrl->dev = dev;
2504
2505 init_completion(&ctrl->done);
2506 init_completion(&ctrl->dma_done);
2507 nand_hw_control_init(&ctrl->controller);
2508 INIT_LIST_HEAD(&ctrl->host_list);
2509
2510 /* Is parameter page in big endian ? */
2511 ctrl->parameter_page_big_endian =
2512 dev_read_u32_default(dev, "parameter-page-big-endian", 1);
2513
2514 /* NAND register range */
2515 #ifndef __UBOOT__
2516 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2517 ctrl->nand_base = devm_ioremap_resource(dev, res);
2518 #else
2519 dev_read_resource(pdev, 0, &res);
2520 ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res));
2521 #endif
2522 if (IS_ERR(ctrl->nand_base))
2523 return PTR_ERR(ctrl->nand_base);
2524
2525 /* Enable clock before using NAND registers */
2526 ctrl->clk = devm_clk_get(dev, "nand");
2527 if (!IS_ERR(ctrl->clk)) {
2528 ret = clk_prepare_enable(ctrl->clk);
2529 if (ret)
2530 return ret;
2531 } else {
2532 ret = PTR_ERR(ctrl->clk);
2533 if (ret == -EPROBE_DEFER)
2534 return ret;
2535
2536 ctrl->clk = NULL;
2537 }
2538
2539 /* Initialize NAND revision */
2540 ret = brcmnand_revision_init(ctrl);
2541 if (ret)
2542 goto err;
2543
2544 /*
2545 * Most chips have this cache at a fixed offset within 'nand' block.
2546 * Some must specify this region separately.
2547 */
2548 #ifndef __UBOOT__
2549 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2550 if (res) {
2551 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2552 if (IS_ERR(ctrl->nand_fc)) {
2553 ret = PTR_ERR(ctrl->nand_fc);
2554 goto err;
2555 }
2556 } else {
2557 ctrl->nand_fc = ctrl->nand_base +
2558 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2559 }
2560 #else
2561 if (!dev_read_resource_byname(pdev, "nand-cache", &res)) {
2562 ctrl->nand_fc = devm_ioremap(dev, res.start,
2563 resource_size(&res));
2564 if (IS_ERR(ctrl->nand_fc)) {
2565 ret = PTR_ERR(ctrl->nand_fc);
2566 goto err;
2567 }
2568 } else {
2569 ctrl->nand_fc = ctrl->nand_base +
2570 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2571 }
2572 #endif
2573
2574 #ifndef __UBOOT__
2575 /* FLASH_DMA */
2576 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2577 if (res) {
2578 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2579 if (IS_ERR(ctrl->flash_dma_base)) {
2580 ret = PTR_ERR(ctrl->flash_dma_base);
2581 goto err;
2582 }
2583
2584 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2585 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2586
2587 /* Allocate descriptor(s) */
2588 ctrl->dma_desc = dmam_alloc_coherent(dev,
2589 sizeof(*ctrl->dma_desc),
2590 &ctrl->dma_pa, GFP_KERNEL);
2591 if (!ctrl->dma_desc) {
2592 ret = -ENOMEM;
2593 goto err;
2594 }
2595
2596 ctrl->dma_irq = platform_get_irq(pdev, 1);
2597 if ((int)ctrl->dma_irq < 0) {
2598 dev_err(dev, "missing FLASH_DMA IRQ\n");
2599 ret = -ENODEV;
2600 goto err;
2601 }
2602
2603 ret = devm_request_irq(dev, ctrl->dma_irq,
2604 brcmnand_dma_irq, 0, DRV_NAME,
2605 ctrl);
2606 if (ret < 0) {
2607 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2608 ctrl->dma_irq, ret);
2609 goto err;
2610 }
2611
2612 dev_info(dev, "enabling FLASH_DMA\n");
2613 }
2614 #endif /* __UBOOT__ */
2615
2616 /* Disable automatic device ID config, direct addressing */
2617 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2618 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2619 /* Disable XOR addressing */
2620 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2621
2622 /* Read the write-protect configuration in the device tree */
2623 wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
2624
2625 if (ctrl->features & BRCMNAND_HAS_WP) {
2626 /* Permanently disable write protection */
2627 if (wp_on == 2)
2628 brcmnand_set_wp(ctrl, false);
2629 } else {
2630 wp_on = 0;
2631 }
2632
2633 #ifndef __UBOOT__
2634 /* IRQ */
2635 ctrl->irq = platform_get_irq(pdev, 0);
2636 if ((int)ctrl->irq < 0) {
2637 dev_err(dev, "no IRQ defined\n");
2638 ret = -ENODEV;
2639 goto err;
2640 }
2641
2642 /*
2643 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2644 * interesting ways
2645 */
2646 if (soc) {
2647 ctrl->soc = soc;
2648
2649 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2650 DRV_NAME, ctrl);
2651
2652 /* Enable interrupt */
2653 ctrl->soc->ctlrdy_ack(ctrl->soc);
2654 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2655 } else {
2656 /* Use standard interrupt infrastructure */
2657 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2658 DRV_NAME, ctrl);
2659 }
2660 if (ret < 0) {
2661 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2662 ctrl->irq, ret);
2663 goto err;
2664 }
2665 #endif /* __UBOOT__ */
2666
2667 #ifndef __UBOOT__
2668 for_each_available_child_of_node(dn, child) {
2669 if (of_device_is_compatible(child, "brcm,nandcs")) {
2670 struct brcmnand_host *host;
2671
2672 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2673 if (!host) {
2674 of_node_put(child);
2675 ret = -ENOMEM;
2676 goto err;
2677 }
2678 host->pdev = pdev;
2679 host->ctrl = ctrl;
2680
2681 ret = brcmnand_init_cs(host, child);
2682 if (ret) {
2683 devm_kfree(dev, host);
2684 continue; /* Try all chip-selects */
2685 }
2686
2687 list_add_tail(&host->node, &ctrl->host_list);
2688 }
2689 }
2690 #else
2691 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
2692 if (ofnode_device_is_compatible(child, "brcm,nandcs")) {
2693 struct brcmnand_host *host;
2694
2695 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2696 if (!host) {
2697 ret = -ENOMEM;
2698 goto err;
2699 }
2700 host->pdev = pdev;
2701 host->ctrl = ctrl;
2702
2703 ret = brcmnand_init_cs(host, child);
2704 if (ret) {
2705 devm_kfree(dev, host);
2706 continue; /* Try all chip-selects */
2707 }
2708
2709 list_add_tail(&host->node, &ctrl->host_list);
2710 }
2711 }
2712 #endif /* __UBOOT__ */
2713
2714 err:
2715 #ifndef __UBOOT__
2716 clk_disable_unprepare(ctrl->clk);
2717 #else
2718 if (ctrl->clk)
2719 clk_disable(ctrl->clk);
2720 #endif /* __UBOOT__ */
2721 return ret;
2722
2723 }
2724 EXPORT_SYMBOL_GPL(brcmnand_probe);
2725
2726 #ifndef __UBOOT__
brcmnand_remove(struct platform_device * pdev)2727 int brcmnand_remove(struct platform_device *pdev)
2728 {
2729 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2730 struct brcmnand_host *host;
2731
2732 list_for_each_entry(host, &ctrl->host_list, node)
2733 nand_release(nand_to_mtd(&host->chip));
2734
2735 clk_disable_unprepare(ctrl->clk);
2736
2737 dev_set_drvdata(&pdev->dev, NULL);
2738
2739 return 0;
2740 }
2741 #else
brcmnand_remove(struct udevice * pdev)2742 int brcmnand_remove(struct udevice *pdev)
2743 {
2744 return 0;
2745 }
2746 #endif /* __UBOOT__ */
2747 EXPORT_SYMBOL_GPL(brcmnand_remove);
2748
2749 MODULE_LICENSE("GPL v2");
2750 MODULE_AUTHOR("Kevin Cernekee");
2751 MODULE_AUTHOR("Brian Norris");
2752 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2753 MODULE_ALIAS("platform:brcmnand");
2754