1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun #include <common.h>
4*4882a593Smuzhiyun #include <asm/io.h>
5*4882a593Smuzhiyun #include <memalign.h>
6*4882a593Smuzhiyun #include <nand.h>
7*4882a593Smuzhiyun #include <linux/errno.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/ioport.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "brcmnand.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct bcm6838_nand_soc {
15*4882a593Smuzhiyun struct brcmnand_soc soc;
16*4882a593Smuzhiyun void __iomem *base;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define BCM6838_NAND_INT 0x00
20*4882a593Smuzhiyun #define BCM6838_NAND_STATUS_SHIFT 0
21*4882a593Smuzhiyun #define BCM6838_NAND_STATUS_MASK (0xfff << BCM6838_NAND_STATUS_SHIFT)
22*4882a593Smuzhiyun #define BCM6838_NAND_ENABLE_SHIFT 16
23*4882a593Smuzhiyun #define BCM6838_NAND_ENABLE_MASK (0xffff << BCM6838_NAND_ENABLE_SHIFT)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun enum {
26*4882a593Smuzhiyun BCM6838_NP_READ = BIT(0),
27*4882a593Smuzhiyun BCM6838_BLOCK_ERASE = BIT(1),
28*4882a593Smuzhiyun BCM6838_COPY_BACK = BIT(2),
29*4882a593Smuzhiyun BCM6838_PAGE_PGM = BIT(3),
30*4882a593Smuzhiyun BCM6838_CTRL_READY = BIT(4),
31*4882a593Smuzhiyun BCM6838_DEV_RBPIN = BIT(5),
32*4882a593Smuzhiyun BCM6838_ECC_ERR_UNC = BIT(6),
33*4882a593Smuzhiyun BCM6838_ECC_ERR_CORR = BIT(7),
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
bcm6838_nand_intc_ack(struct brcmnand_soc * soc)36*4882a593Smuzhiyun static bool bcm6838_nand_intc_ack(struct brcmnand_soc *soc)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct bcm6838_nand_soc *priv =
39*4882a593Smuzhiyun container_of(soc, struct bcm6838_nand_soc, soc);
40*4882a593Smuzhiyun void __iomem *mmio = priv->base + BCM6838_NAND_INT;
41*4882a593Smuzhiyun u32 val = brcmnand_readl(mmio);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (val & (BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT)) {
44*4882a593Smuzhiyun /* Ack interrupt */
45*4882a593Smuzhiyun val &= ~BCM6838_NAND_STATUS_MASK;
46*4882a593Smuzhiyun val |= BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT;
47*4882a593Smuzhiyun brcmnand_writel(val, mmio);
48*4882a593Smuzhiyun return true;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return false;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
bcm6838_nand_intc_set(struct brcmnand_soc * soc,bool en)54*4882a593Smuzhiyun static void bcm6838_nand_intc_set(struct brcmnand_soc *soc, bool en)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct bcm6838_nand_soc *priv =
57*4882a593Smuzhiyun container_of(soc, struct bcm6838_nand_soc, soc);
58*4882a593Smuzhiyun void __iomem *mmio = priv->base + BCM6838_NAND_INT;
59*4882a593Smuzhiyun u32 val = brcmnand_readl(mmio);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Don't ack any interrupts */
62*4882a593Smuzhiyun val &= ~BCM6838_NAND_STATUS_MASK;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (en)
65*4882a593Smuzhiyun val |= BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT;
66*4882a593Smuzhiyun else
67*4882a593Smuzhiyun val &= ~(BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun brcmnand_writel(val, mmio);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
bcm6838_nand_probe(struct udevice * dev)72*4882a593Smuzhiyun static int bcm6838_nand_probe(struct udevice *dev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct udevice *pdev = dev;
75*4882a593Smuzhiyun struct bcm6838_nand_soc *priv = dev_get_priv(dev);
76*4882a593Smuzhiyun struct brcmnand_soc *soc;
77*4882a593Smuzhiyun struct resource res;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun soc = &priv->soc;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun dev_read_resource_byname(pdev, "nand-int-base", &res);
82*4882a593Smuzhiyun priv->base = ioremap(res.start, resource_size(&res));
83*4882a593Smuzhiyun if (IS_ERR(priv->base))
84*4882a593Smuzhiyun return PTR_ERR(priv->base);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun soc->ctlrdy_ack = bcm6838_nand_intc_ack;
87*4882a593Smuzhiyun soc->ctlrdy_set_enabled = bcm6838_nand_intc_set;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Disable and ack all interrupts */
90*4882a593Smuzhiyun brcmnand_writel(0, priv->base + BCM6838_NAND_INT);
91*4882a593Smuzhiyun brcmnand_writel(BCM6838_NAND_STATUS_MASK,
92*4882a593Smuzhiyun priv->base + BCM6838_NAND_INT);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return brcmnand_probe(pdev, soc);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct udevice_id bcm6838_nand_dt_ids[] = {
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun .compatible = "brcm,nand-bcm6838",
100*4882a593Smuzhiyun },
101*4882a593Smuzhiyun { /* sentinel */ }
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun U_BOOT_DRIVER(bcm6838_nand) = {
105*4882a593Smuzhiyun .name = "bcm6838-nand",
106*4882a593Smuzhiyun .id = UCLASS_MTD,
107*4882a593Smuzhiyun .of_match = bcm6838_nand_dt_ids,
108*4882a593Smuzhiyun .probe = bcm6838_nand_probe,
109*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct bcm6838_nand_soc),
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
board_nand_init(void)112*4882a593Smuzhiyun void board_nand_init(void)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun struct udevice *dev;
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun ret = uclass_get_device_by_driver(UCLASS_MTD,
118*4882a593Smuzhiyun DM_GET_DRIVER(bcm6838_nand), &dev);
119*4882a593Smuzhiyun if (ret && ret != -ENODEV)
120*4882a593Smuzhiyun pr_err("Failed to initialize %s. (error %d)\n", dev->name,
121*4882a593Smuzhiyun ret);
122*4882a593Smuzhiyun }
123