1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2013 - 2015 Xilinx, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Xilinx Zynq SD Host Controller Interface
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <clk.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <fdtdec.h>
13*4882a593Smuzhiyun #include <linux/libfdt.h>
14*4882a593Smuzhiyun #include <malloc.h>
15*4882a593Smuzhiyun #include <sdhci.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
20*4882a593Smuzhiyun # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct arasan_sdhci_plat {
24*4882a593Smuzhiyun struct mmc_config cfg;
25*4882a593Smuzhiyun struct mmc mmc;
26*4882a593Smuzhiyun unsigned int f_max;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
arasan_sdhci_probe(struct udevice * dev)29*4882a593Smuzhiyun static int arasan_sdhci_probe(struct udevice *dev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
32*4882a593Smuzhiyun struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
33*4882a593Smuzhiyun struct sdhci_host *host = dev_get_priv(dev);
34*4882a593Smuzhiyun struct clk clk;
35*4882a593Smuzhiyun unsigned long clock;
36*4882a593Smuzhiyun int ret;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &clk);
39*4882a593Smuzhiyun if (ret < 0) {
40*4882a593Smuzhiyun dev_err(dev, "failed to get clock\n");
41*4882a593Smuzhiyun return ret;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun clock = clk_get_rate(&clk);
45*4882a593Smuzhiyun if (IS_ERR_VALUE(clock)) {
46*4882a593Smuzhiyun dev_err(dev, "failed to get rate\n");
47*4882a593Smuzhiyun return clock;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun debug("%s: CLK %ld\n", __func__, clock);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun ret = clk_enable(&clk);
52*4882a593Smuzhiyun if (ret && ret != -ENOSYS) {
53*4882a593Smuzhiyun dev_err(dev, "failed to enable clock\n");
54*4882a593Smuzhiyun return ret;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
58*4882a593Smuzhiyun SDHCI_QUIRK_BROKEN_R1B;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef CONFIG_ZYNQ_HISPD_BROKEN
61*4882a593Smuzhiyun host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun host->max_clk = clock;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
67*4882a593Smuzhiyun CONFIG_ZYNQ_SDHCI_MIN_FREQ);
68*4882a593Smuzhiyun host->mmc = &plat->mmc;
69*4882a593Smuzhiyun if (ret)
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun host->mmc->priv = host;
72*4882a593Smuzhiyun host->mmc->dev = dev;
73*4882a593Smuzhiyun upriv->mmc = host->mmc;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return sdhci_probe(dev);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
arasan_sdhci_ofdata_to_platdata(struct udevice * dev)78*4882a593Smuzhiyun static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
81*4882a593Smuzhiyun struct sdhci_host *host = dev_get_priv(dev);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun host->name = dev->name;
84*4882a593Smuzhiyun host->ioaddr = (void *)devfdt_get_addr(dev);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
87*4882a593Smuzhiyun "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
arasan_sdhci_bind(struct udevice * dev)92*4882a593Smuzhiyun static int arasan_sdhci_bind(struct udevice *dev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return sdhci_bind(dev, &plat->mmc, &plat->cfg);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct udevice_id arasan_sdhci_ids[] = {
100*4882a593Smuzhiyun { .compatible = "arasan,sdhci-8.9a" },
101*4882a593Smuzhiyun { }
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun U_BOOT_DRIVER(arasan_sdhci_drv) = {
105*4882a593Smuzhiyun .name = "arasan_sdhci",
106*4882a593Smuzhiyun .id = UCLASS_MMC,
107*4882a593Smuzhiyun .of_match = arasan_sdhci_ids,
108*4882a593Smuzhiyun .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
109*4882a593Smuzhiyun .ops = &sdhci_ops,
110*4882a593Smuzhiyun .bind = arasan_sdhci_bind,
111*4882a593Smuzhiyun .probe = arasan_sdhci_probe,
112*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct sdhci_host),
113*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
114*4882a593Smuzhiyun };
115