1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <dm/device.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/sizes.h>
11*4882a593Smuzhiyun #include <malloc.h>
12*4882a593Smuzhiyun #include <mmc.h>
13*4882a593Smuzhiyun #include <sdhci.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SDHCI_TANGIER_FMAX 200000000
16*4882a593Smuzhiyun #define SDHCI_TANGIER_FMIN 400000
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct sdhci_tangier_plat {
19*4882a593Smuzhiyun struct mmc_config cfg;
20*4882a593Smuzhiyun struct mmc mmc;
21*4882a593Smuzhiyun void __iomem *ioaddr;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
sdhci_tangier_bind(struct udevice * dev)24*4882a593Smuzhiyun static int sdhci_tangier_bind(struct udevice *dev)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return sdhci_bind(dev, &plat->mmc, &plat->cfg);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
sdhci_tangier_probe(struct udevice * dev)31*4882a593Smuzhiyun static int sdhci_tangier_probe(struct udevice *dev)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
34*4882a593Smuzhiyun struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
35*4882a593Smuzhiyun struct sdhci_host *host = dev_get_priv(dev);
36*4882a593Smuzhiyun fdt_addr_t base;
37*4882a593Smuzhiyun int ret;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun base = devfdt_get_addr(dev);
40*4882a593Smuzhiyun if (base == FDT_ADDR_T_NONE)
41*4882a593Smuzhiyun return -EINVAL;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun plat->ioaddr = devm_ioremap(dev, base, SZ_1K);
44*4882a593Smuzhiyun if (!plat->ioaddr)
45*4882a593Smuzhiyun return -ENOMEM;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun host->name = dev->name;
48*4882a593Smuzhiyun host->ioaddr = plat->ioaddr;
49*4882a593Smuzhiyun host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
50*4882a593Smuzhiyun SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */
53*4882a593Smuzhiyun host->voltages = MMC_VDD_165_195;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ret = sdhci_setup_cfg(&plat->cfg, host, SDHCI_TANGIER_FMAX,
56*4882a593Smuzhiyun SDHCI_TANGIER_FMIN);
57*4882a593Smuzhiyun if (ret)
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun upriv->mmc = &plat->mmc;
61*4882a593Smuzhiyun host->mmc = &plat->mmc;
62*4882a593Smuzhiyun host->mmc->priv = host;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return sdhci_probe(dev);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct udevice_id sdhci_tangier_match[] = {
68*4882a593Smuzhiyun { .compatible = "intel,sdhci-tangier" },
69*4882a593Smuzhiyun { /* sentinel */ }
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun U_BOOT_DRIVER(sdhci_tangier) = {
73*4882a593Smuzhiyun .name = "sdhci-tangier",
74*4882a593Smuzhiyun .id = UCLASS_MMC,
75*4882a593Smuzhiyun .of_match = sdhci_tangier_match,
76*4882a593Smuzhiyun .bind = sdhci_tangier_bind,
77*4882a593Smuzhiyun .probe = sdhci_tangier_probe,
78*4882a593Smuzhiyun .ops = &sdhci_ops,
79*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct sdhci_host),
80*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct sdhci_tangier_plat),
81*4882a593Smuzhiyun };
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