1 /*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10
11 #include <common.h>
12 #include <errno.h>
13 #include <malloc.h>
14 #include <mmc.h>
15 #include <sdhci.h>
16
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
19 #else
20 void *aligned_buffer;
21 #endif
22
sdhci_reset(struct sdhci_host * host,u8 mask)23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
24 {
25 unsigned long timeout;
26
27 /* Wait max 100 ms */
28 timeout = 100;
29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
31 if (timeout == 0) {
32 printf("%s: Reset 0x%x never completed.\n",
33 __func__, (int)mask);
34 return;
35 }
36 timeout--;
37 udelay(1000);
38 }
39 }
40
sdhci_cmd_done(struct sdhci_host * host,struct mmc_cmd * cmd)41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
42 {
43 int i;
44 if (cmd->resp_type & MMC_RSP_136) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i = 0; i < 4; i++) {
47 cmd->response[i] = sdhci_readl(host,
48 SDHCI_RESPONSE + (3-i)*4) << 8;
49 if (i != 3)
50 cmd->response[i] |= sdhci_readb(host,
51 SDHCI_RESPONSE + (3-i)*4-1);
52 }
53 } else {
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
55 }
56 }
57
sdhci_transfer_pio(struct sdhci_host * host,struct mmc_data * data)58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
59 {
60 int i;
61 char *offs;
62 for (i = 0; i < data->blocksize; i += 4) {
63 offs = data->dest + i;
64 if (data->flags == MMC_DATA_READ)
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
66 else
67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
68 }
69 }
70
sdhci_transfer_data(struct sdhci_host * host,struct mmc_data * data,unsigned int start_addr)71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
72 unsigned int start_addr)
73 {
74 unsigned int stat, rdy, mask, timeout, block = 0;
75 bool transfer_done = false;
76 #ifdef CONFIG_MMC_SDHCI_SDMA
77 unsigned char ctrl;
78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
79 ctrl &= ~SDHCI_CTRL_DMA_MASK;
80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
81 #endif
82
83 timeout = 1000000;
84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
86 do {
87 stat = sdhci_readl(host, SDHCI_INT_STATUS);
88 if (stat & SDHCI_INT_ERROR) {
89 printf("%s: Error detected in status(0x%X)!\n",
90 __func__, stat);
91 return -EIO;
92 }
93 if (!transfer_done && (stat & rdy)) {
94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
95 continue;
96 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
97 sdhci_transfer_pio(host, data);
98 data->dest += data->blocksize;
99 if (++block >= data->blocks) {
100 /* Keep looping until the SDHCI_INT_DATA_END is
101 * cleared, even if we finished sending all the
102 * blocks.
103 */
104 transfer_done = true;
105 continue;
106 }
107 }
108 #ifdef CONFIG_MMC_SDHCI_SDMA
109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
114 }
115 #endif
116 if (timeout-- > 0)
117 udelay(10);
118 else {
119 printf("%s: Transfer data timeout\n", __func__);
120 return -ETIMEDOUT;
121 }
122 } while (!(stat & SDHCI_INT_DATA_END));
123 return 0;
124 }
125
126 /*
127 * No command will be sent by driver if card is busy, so driver must wait
128 * for card ready state.
129 * Every time when card is busy after timeout then (last) timeout value will be
130 * increased twice but only if it doesn't exceed global defined maximum.
131 * Each function call will use last timeout value.
132 */
133 #define SDHCI_CMD_MAX_TIMEOUT 3200
134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
135 #define SDHCI_READ_STATUS_TIMEOUT 1000
136
137 #ifdef CONFIG_DM_MMC
sdhci_send_command(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
139 struct mmc_data *data)
140 {
141 struct mmc *mmc = mmc_get_mmc_dev(dev);
142
143 #else
144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
145 struct mmc_data *data)
146 {
147 #endif
148 struct sdhci_host *host = mmc->priv;
149 unsigned int stat = 0;
150 int ret = 0;
151 int trans_bytes = 0, is_aligned = 1;
152 u32 mask, flags, mode;
153 unsigned int time = 0, start_addr = 0;
154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
155 unsigned start = get_timer(0);
156
157 /* Timeout unit - ms */
158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
159
160 mask = SDHCI_CMD_INHIBIT;
161
162 if (data)
163 mask |= SDHCI_DATA_INHIBIT;
164
165 /* We shouldn't wait for data inihibit for stop commands, even
166 though they might use busy signaling */
167 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
168 mask &= ~SDHCI_DATA_INHIBIT;
169
170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
171 if (time >= cmd_timeout) {
172 printf("%s: MMC: %d busy ", __func__, mmc_dev);
173 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
174 cmd_timeout += cmd_timeout;
175 printf("timeout increasing to: %u ms.\n",
176 cmd_timeout);
177 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
178 } else {
179 puts("timeout.\n");
180 /* remove timeout return error and try to send command */
181 break;
182 }
183 }
184 time++;
185 udelay(1000);
186 }
187
188 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
189
190 mask = SDHCI_INT_RESPONSE;
191 if (!(cmd->resp_type & MMC_RSP_PRESENT))
192 flags = SDHCI_CMD_RESP_NONE;
193 else if (cmd->resp_type & MMC_RSP_136)
194 flags = SDHCI_CMD_RESP_LONG;
195 else if (cmd->resp_type & MMC_RSP_BUSY) {
196 flags = SDHCI_CMD_RESP_SHORT_BUSY;
197 if (data)
198 mask |= SDHCI_INT_DATA_END;
199 } else
200 flags = SDHCI_CMD_RESP_SHORT;
201
202 if (cmd->resp_type & MMC_RSP_CRC)
203 flags |= SDHCI_CMD_CRC;
204 if (cmd->resp_type & MMC_RSP_OPCODE)
205 flags |= SDHCI_CMD_INDEX;
206 if (data)
207 flags |= SDHCI_CMD_DATA;
208
209 if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK ||
210 cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) {
211 mask &= ~SDHCI_INT_RESPONSE;
212 mask |= SDHCI_INT_DATA_AVAIL;
213 flags |= SDHCI_CMD_DATA;
214 }
215
216 /* Set Transfer mode regarding to data flag */
217 if (data != 0) {
218 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
219 mode = SDHCI_TRNS_BLK_CNT_EN;
220 trans_bytes = data->blocks * data->blocksize;
221 if (data->blocks > 1)
222 mode |= SDHCI_TRNS_MULTI;
223
224 if (data->flags == MMC_DATA_READ)
225 mode |= SDHCI_TRNS_READ;
226
227 #ifdef CONFIG_MMC_SDHCI_SDMA
228 if (data->flags == MMC_DATA_READ)
229 start_addr = (unsigned long)data->dest;
230 else
231 start_addr = (unsigned long)data->src;
232 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
233 (start_addr & 0x7) != 0x0) {
234 is_aligned = 0;
235 start_addr = (unsigned long)aligned_buffer;
236 if (data->flags != MMC_DATA_READ)
237 memcpy(aligned_buffer, data->src, trans_bytes);
238 }
239
240 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
241 /*
242 * Always use this bounce-buffer when
243 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
244 */
245 is_aligned = 0;
246 start_addr = (unsigned long)aligned_buffer;
247 if (data->flags != MMC_DATA_READ)
248 memcpy(aligned_buffer, data->src, trans_bytes);
249 #endif
250
251 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
252 mode |= SDHCI_TRNS_DMA;
253 #endif
254 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
255 data->blocksize),
256 SDHCI_BLOCK_SIZE);
257 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
258 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
259 } else if (cmd->resp_type & MMC_RSP_BUSY) {
260 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
261 }
262
263 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
264 #ifdef CONFIG_MMC_SDHCI_SDMA
265 if (data != 0) {
266 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
267 flush_cache(start_addr, trans_bytes);
268 }
269 #endif
270 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
271 start = get_timer(0);
272 do {
273 stat = sdhci_readl(host, SDHCI_INT_STATUS);
274 if (stat & SDHCI_INT_ERROR)
275 break;
276
277 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
278 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
279 return 0;
280 } else {
281 printf("%s: Timeout for status update!\n",
282 __func__);
283 return -ETIMEDOUT;
284 }
285 }
286 } while ((stat & mask) != mask);
287
288 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
289 sdhci_cmd_done(host, cmd);
290 sdhci_writel(host, mask, SDHCI_INT_STATUS);
291 } else
292 ret = -1;
293
294 if (!ret && data)
295 ret = sdhci_transfer_data(host, data, start_addr);
296
297 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
298 udelay(1000);
299
300 stat = sdhci_readl(host, SDHCI_INT_STATUS);
301 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
302 if (!ret) {
303 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
304 !is_aligned && (data->flags == MMC_DATA_READ))
305 memcpy(data->dest, aligned_buffer, trans_bytes);
306 return 0;
307 }
308
309 sdhci_reset(host, SDHCI_RESET_CMD);
310 sdhci_reset(host, SDHCI_RESET_DATA);
311 if (stat & SDHCI_INT_TIMEOUT)
312 return -ETIMEDOUT;
313 else
314 return -ECOMM;
315 }
316
317 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
318 {
319 unsigned int timeout;
320
321 clk |= SDHCI_CLOCK_INT_EN;
322 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
323
324 /* Wait max 20 ms */
325 timeout = 20;
326 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
327 & SDHCI_CLOCK_INT_STABLE)) {
328 if (timeout == 0) {
329 printf("%s: Internal clock never stabilised.\n",
330 __func__);
331 return;
332 }
333 timeout--;
334 udelay(1000);
335 }
336 clk |= SDHCI_CLOCK_CARD_EN;
337 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
338 }
339
340 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
341 {
342 unsigned int div, clk = 0, timeout;
343
344 /* Wait max 20 ms */
345 timeout = 200;
346 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
347 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
348 if (timeout == 0) {
349 printf("%s: Timeout to wait cmd & data inhibit\n",
350 __func__);
351 return -EBUSY;
352 }
353
354 timeout--;
355 udelay(100);
356 }
357 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
358
359 if (clock == 0)
360 return 0;
361 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
362 /*
363 * Check if the Host Controller supports Programmable Clock
364 * Mode.
365 */
366 if (host->clk_mul) {
367 for (div = 1; div <= 1024; div++) {
368 if ((host->max_clk / div) <= clock)
369 break;
370 }
371
372 /*
373 * Set Programmable Clock Mode in the Clock
374 * Control register.
375 */
376 clk = SDHCI_PROG_CLOCK_MODE;
377 div--;
378 } else {
379 /* Version 3.00 divisors must be a multiple of 2. */
380 if (host->max_clk <= clock) {
381 div = 1;
382 } else {
383 for (div = 2;
384 div < SDHCI_MAX_DIV_SPEC_300;
385 div += 2) {
386 if ((host->max_clk / div) <= clock)
387 break;
388 }
389 }
390 div >>= 1;
391 }
392 } else {
393 /* Version 2.00 divisors must be a power of 2. */
394 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
395 if ((host->max_clk / div) <= clock)
396 break;
397 }
398 div >>= 1;
399 }
400 if (host->ops && host->ops->set_clock_ext)
401 host->ops->set_clock_ext(host, div);
402
403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
405 << SDHCI_DIVIDER_HI_SHIFT;
406
407 sdhci_enable_clk(host, clk);
408
409 host->clock = clock;
410 return 0;
411 }
412
413 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
414 {
415 u8 pwr = 0;
416
417 if (power != (unsigned short)-1) {
418 switch (1 << power) {
419 case MMC_VDD_165_195:
420 pwr = SDHCI_POWER_180;
421 break;
422 case MMC_VDD_29_30:
423 case MMC_VDD_30_31:
424 pwr = SDHCI_POWER_300;
425 break;
426 case MMC_VDD_32_33:
427 case MMC_VDD_33_34:
428 pwr = SDHCI_POWER_330;
429 break;
430 }
431 }
432
433 if (pwr == 0) {
434 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
435 return;
436 }
437
438 pwr |= SDHCI_POWER_ON;
439
440 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
441 }
442
443 static void sdhci_set_uhs_signaling(struct sdhci_host *host)
444 {
445 u16 ctrl_2;
446 u32 timing = host->mmc->timing;
447
448 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
449 /* Select Bus Speed Mode for host */
450 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
451
452 if ((timing != MMC_TIMING_LEGACY) &&
453 (timing != MMC_TIMING_MMC_HS) &&
454 (timing != MMC_TIMING_SD_HS))
455 ctrl_2 |= SDHCI_CTRL_VDD_180;
456
457 if ((timing == MMC_TIMING_MMC_HS200) ||
458 (timing == MMC_TIMING_UHS_SDR104))
459 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A;
460 else if (timing == MMC_TIMING_UHS_SDR12)
461 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
462 else if (timing == MMC_TIMING_UHS_SDR25)
463 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
464 else if ((timing == MMC_TIMING_UHS_SDR50) ||
465 (timing == MMC_TIMING_MMC_HS))
466 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
467 else if ((timing == MMC_TIMING_UHS_DDR50) ||
468 (timing == MMC_TIMING_MMC_DDR52))
469 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
470 else if (timing == MMC_TIMING_MMC_HS400 ||
471 timing == MMC_TIMING_MMC_HS400ES)
472 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A;
473
474 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
475 }
476
477 #ifdef CONFIG_DM_MMC
478 static bool sdhci_card_busy(struct udevice *dev)
479 {
480 struct mmc *mmc = mmc_get_mmc_dev(dev);
481 #else
482 static bool sdhci_card_busy(struct mmc *mmc)
483 {
484 #endif
485 struct sdhci_host *host = mmc->priv;
486 u32 present_state;
487
488 /* Check whether DAT[0] is 0 */
489 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
490
491 return !(present_state & SDHCI_DATA_0_LVL);
492 }
493
494 #ifdef CONFIG_DM_MMC
495 static int sdhci_set_ios(struct udevice *dev)
496 {
497 struct mmc *mmc = mmc_get_mmc_dev(dev);
498 #else
499 static int sdhci_set_ios(struct mmc *mmc)
500 {
501 #endif
502 u32 ctrl;
503 struct sdhci_host *host = mmc->priv;
504
505 if (host->ops && host->ops->set_control_reg)
506 host->ops->set_control_reg(host);
507
508 if (mmc->clock != host->clock) {
509 if (host->ops && host->ops->set_clock)
510 host->ops->set_clock(host, mmc->clock);
511 else
512 sdhci_set_clock(host, mmc->clock);
513 }
514
515 /* Set bus width */
516 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
517 if (mmc->bus_width == 8) {
518 ctrl &= ~SDHCI_CTRL_4BITBUS;
519 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
520 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
521 ctrl |= SDHCI_CTRL_8BITBUS;
522 } else {
523 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
524 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
525 ctrl &= ~SDHCI_CTRL_8BITBUS;
526 if (mmc->bus_width == 4)
527 ctrl |= SDHCI_CTRL_4BITBUS;
528 else
529 ctrl &= ~SDHCI_CTRL_4BITBUS;
530 }
531
532 if (!(mmc->timing == MMC_TIMING_LEGACY) &&
533 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
534 ctrl |= SDHCI_CTRL_HISPD;
535 else
536 ctrl &= ~SDHCI_CTRL_HISPD;
537
538 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
539
540 if ((mmc->timing != MMC_TIMING_LEGACY) &&
541 (mmc->timing != MMC_TIMING_MMC_HS) &&
542 (mmc->timing != MMC_TIMING_SD_HS))
543 sdhci_set_power(host, MMC_VDD_165_195_SHIFT);
544
545 sdhci_set_uhs_signaling(host);
546
547 /* If available, call the driver specific "post" set_ios() function */
548 if (host->ops && host->ops->set_ios_post)
549 host->ops->set_ios_post(host);
550
551 return 0;
552 }
553
554 static int sdhci_init(struct mmc *mmc)
555 {
556 struct sdhci_host *host = mmc->priv;
557
558 sdhci_reset(host, SDHCI_RESET_ALL);
559
560 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
561 aligned_buffer = memalign(8, 512*1024);
562 if (!aligned_buffer) {
563 printf("%s: Aligned buffer alloc failed!!!\n",
564 __func__);
565 return -ENOMEM;
566 }
567 }
568
569 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
570
571 if (host->ops && host->ops->get_cd)
572 host->ops->get_cd(host);
573
574 /* Enable only interrupts served by the SD controller */
575 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
576 SDHCI_INT_ENABLE);
577 /* Mask all sdhci interrupt sources */
578 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
579
580 return 0;
581 }
582
583 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
584 {
585 struct mmc_cmd cmd;
586
587 cmd.cmdidx = opcode;
588 cmd.resp_type = MMC_RSP_R1;
589 cmd.cmdarg = 0;
590 /*
591 * In response to CMD19, the card sends 64 bytes of tuning
592 * block to the Host Controller. So we set the block size
593 * to 64 here.
594 */
595 if (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
596 host->mmc->bus_width == MMC_BUS_WIDTH_8BIT)
597 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
598 else
599 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
600
601 /*
602 * The tuning block is sent by the card to the host controller.
603 * So we set the TRNS_READ bit in the Transfer Mode register.
604 * This also takes care of setting DMA Enable and Multi Block
605 * Select in the same register to 0.
606 */
607 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
608
609 #ifdef CONFIG_DM_MMC
610 return sdhci_send_command(host->mmc->dev, &cmd, NULL);
611 #else
612 return sdhci_send_command(host->mmc, &cmd, NULL);
613 #endif
614 }
615
616 #define MAX_TUNING_LOOP 40
617 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
618 {
619 int i;
620 int ret;
621
622 /*
623 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
624 * of loops reaches 40 times.
625 */
626 for (i = 0; i < MAX_TUNING_LOOP; i++) {
627 u16 ctrl;
628
629 ret = sdhci_send_tuning(host, opcode);
630
631 if (ret)
632 return ret;
633
634 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
635 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
636 if (ctrl & SDHCI_CTRL_TUNED_CLK)
637 /* Tuning successfully */
638 return 0;
639 break;
640 }
641 }
642
643 return -ETIMEDOUT;
644 }
645
646 #ifdef CONFIG_DM_MMC
647 static int sdhci_execute_tuning(struct udevice *dev, u32 opcode)
648 {
649 struct mmc *mmc = mmc_get_mmc_dev(dev);
650 #else
651 static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode)
652 {
653 #endif
654 struct sdhci_host *host = mmc->priv;
655 u16 ctrl;
656
657 /*
658 * The Host Controller needs tuning in case of SDR104 and DDR50
659 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
660 * the Capabilities register.
661 * If the Host Controller supports the HS200 mode then the
662 * tuning function has to be executed.
663 */
664 switch (mmc->timing) {
665 /* HS400 tuning is done in HS200 mode */
666 case MMC_TIMING_MMC_HS400:
667 return -EINVAL;
668 case MMC_TIMING_MMC_HS200:
669 /*
670 * Periodic re-tuning for HS400 is not expected to be needed, so
671 * disable it here.
672 */
673 break;
674 default:
675 return -EINVAL;
676 }
677
678 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
679 ctrl |= SDHCI_CTRL_EXEC_TUNING;
680 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
681
682 return __sdhci_execute_tuning(host, opcode);
683 }
684
685 #ifdef CONFIG_DM_MMC
686 int sdhci_probe(struct udevice *dev)
687 {
688 struct mmc *mmc = mmc_get_mmc_dev(dev);
689
690 return sdhci_init(mmc);
691 }
692
693 static int sdhci_set_enhanced_strobe(struct udevice *dev)
694 {
695 struct mmc *mmc = mmc_get_mmc_dev(dev);
696 struct sdhci_host *host = mmc->priv;
697
698 if (host->ops && host->ops->set_enhanced_strobe)
699 return host->ops->set_enhanced_strobe(host);
700
701 return -ENOTSUPP;
702 }
703
704 const struct dm_mmc_ops sdhci_ops = {
705 .card_busy = sdhci_card_busy,
706 .send_cmd = sdhci_send_command,
707 .set_ios = sdhci_set_ios,
708 .execute_tuning = sdhci_execute_tuning,
709 .set_enhanced_strobe = sdhci_set_enhanced_strobe,
710 };
711 #else
712 static const struct mmc_ops sdhci_ops = {
713 .card_busy = sdhci_card_busy,
714 .send_cmd = sdhci_send_command,
715 .set_ios = sdhci_set_ios,
716 .init = sdhci_init,
717 .execute_tuning = sdhci_execute_tuning,
718 };
719 #endif
720
721 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
722 u32 f_max, u32 f_min)
723 {
724 u32 caps, caps_1;
725
726 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
727
728 #ifdef CONFIG_MMC_SDHCI_SDMA
729 if (!(caps & SDHCI_CAN_DO_SDMA)) {
730 printf("%s: Your controller doesn't support SDMA!!\n",
731 __func__);
732 return -EINVAL;
733 }
734 #endif
735 if (host->quirks & SDHCI_QUIRK_REG32_RW)
736 host->version =
737 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
738 else
739 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
740
741 cfg->name = host->name;
742 #ifndef CONFIG_DM_MMC
743 cfg->ops = &sdhci_ops;
744 #endif
745
746 /* Check whether the clock multiplier is supported or not */
747 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
748 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
749 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
750 SDHCI_CLOCK_MUL_SHIFT;
751 }
752
753 if (host->max_clk == 0) {
754 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
755 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
756 SDHCI_CLOCK_BASE_SHIFT;
757 else
758 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
759 SDHCI_CLOCK_BASE_SHIFT;
760 host->max_clk *= 1000000;
761 if (host->clk_mul)
762 host->max_clk *= host->clk_mul;
763 }
764 if (host->max_clk == 0) {
765 printf("%s: Hardware doesn't specify base clock frequency\n",
766 __func__);
767 return -EINVAL;
768 }
769 if (f_max && (f_max < host->max_clk))
770 cfg->f_max = f_max;
771 else
772 cfg->f_max = host->max_clk;
773 if (f_min)
774 cfg->f_min = f_min;
775 else {
776 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
777 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
778 else
779 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
780 }
781 cfg->voltages = 0;
782 if (caps & SDHCI_CAN_VDD_330)
783 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
784 if (caps & SDHCI_CAN_VDD_300)
785 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
786 if (caps & SDHCI_CAN_VDD_180)
787 cfg->voltages |= MMC_VDD_165_195;
788
789 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
790 cfg->voltages |= host->voltages;
791
792 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
793
794 /* Since Host Controller Version3.0 */
795 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
796 if (!(caps & SDHCI_CAN_DO_8BIT))
797 cfg->host_caps &= ~MMC_MODE_8BIT;
798 }
799
800 if (host->host_caps)
801 cfg->host_caps |= host->host_caps;
802
803 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
804
805 return 0;
806 }
807
808 #ifdef CONFIG_BLK
809 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
810 {
811 return mmc_bind(dev, mmc, cfg);
812 }
813 #else
814 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
815 {
816 int ret;
817
818 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
819 if (ret)
820 return ret;
821
822 host->mmc = mmc_create(&host->cfg, host);
823 if (host->mmc == NULL) {
824 printf("%s: mmc create fail!\n", __func__);
825 return -ENOMEM;
826 }
827
828 return 0;
829 }
830 #endif
831