1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Marvell SD Host Controller Interface
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <malloc.h>
9*4882a593Smuzhiyun #include <sdhci.h>
10*4882a593Smuzhiyun #include <linux/mbus.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
13*4882a593Smuzhiyun #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
14*4882a593Smuzhiyun
sdhci_mvebu_mbus_config(void __iomem * base)15*4882a593Smuzhiyun static void sdhci_mvebu_mbus_config(void __iomem *base)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun const struct mbus_dram_target_info *dram;
18*4882a593Smuzhiyun int i;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun dram = mvebu_mbus_dram_info();
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
23*4882a593Smuzhiyun writel(0, base + SDHCI_WINDOW_CTRL(i));
24*4882a593Smuzhiyun writel(0, base + SDHCI_WINDOW_BASE(i));
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun for (i = 0; i < dram->num_cs; i++) {
28*4882a593Smuzhiyun const struct mbus_dram_window *cs = dram->cs + i;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Write size, attributes and target id to control register */
31*4882a593Smuzhiyun writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
32*4882a593Smuzhiyun (dram->mbus_dram_target_id << 4) | 1,
33*4882a593Smuzhiyun base + SDHCI_WINDOW_CTRL(i));
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Write base address to base register */
36*4882a593Smuzhiyun writel(cs->base, base + SDHCI_WINDOW_BASE(i));
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
41*4882a593Smuzhiyun static struct sdhci_ops mv_ops;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #if defined(CONFIG_SHEEVA_88SV331xV5)
44*4882a593Smuzhiyun #define SD_CE_ATA_2 0xEA
45*4882a593Smuzhiyun #define MMC_CARD 0x1000
46*4882a593Smuzhiyun #define MMC_WIDTH 0x0100
mv_sdhci_writeb(struct sdhci_host * host,u8 val,int reg)47*4882a593Smuzhiyun static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct mmc *mmc = host->mmc;
50*4882a593Smuzhiyun u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
53*4882a593Smuzhiyun if (mmc->bus_width == 8)
54*4882a593Smuzhiyun writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
55*4882a593Smuzhiyun else
56*4882a593Smuzhiyun writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun writeb(val, host->ioaddr + reg);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #else
63*4882a593Smuzhiyun #define mv_sdhci_writeb NULL
64*4882a593Smuzhiyun #endif /* CONFIG_SHEEVA_88SV331xV5 */
65*4882a593Smuzhiyun #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static char *MVSDH_NAME = "mv_sdh";
mv_sdh_init(unsigned long regbase,u32 max_clk,u32 min_clk,u32 quirks)68*4882a593Smuzhiyun int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct sdhci_host *host = NULL;
71*4882a593Smuzhiyun host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
72*4882a593Smuzhiyun if (!host) {
73*4882a593Smuzhiyun printf("sdh_host malloc fail!\n");
74*4882a593Smuzhiyun return -ENOMEM;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun host->name = MVSDH_NAME;
78*4882a593Smuzhiyun host->ioaddr = (void *)regbase;
79*4882a593Smuzhiyun host->quirks = quirks;
80*4882a593Smuzhiyun host->max_clk = max_clk;
81*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
82*4882a593Smuzhiyun memset(&mv_ops, 0, sizeof(struct sdhci_ops));
83*4882a593Smuzhiyun mv_ops.write_b = mv_sdhci_writeb;
84*4882a593Smuzhiyun host->ops = &mv_ops;
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
88*4882a593Smuzhiyun /* Configure SDHCI MBUS mbus bridge windows */
89*4882a593Smuzhiyun sdhci_mvebu_mbus_config((void __iomem *)regbase);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return add_sdhci(host, 0, min_clk);
93*4882a593Smuzhiyun }
94