1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) Copyright 2018 Cisco Systems, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <mach/sdhci.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <sdhci.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * The BCMSTB SDHCI has a quirk in that its actual maximum frequency
15*4882a593Smuzhiyun * capability is 100 MHz. The divisor that is eventually written to
16*4882a593Smuzhiyun * SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
17*4882a593Smuzhiyun * reports, and relative to this maximum frequency.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * This define used to be set to 52000000 (52 MHz), the desired
20*4882a593Smuzhiyun * maximum frequency, but that would result in the communication
21*4882a593Smuzhiyun * actually running at 100 MHz (seemingly without issue), which is
22*4882a593Smuzhiyun * out-of-spec.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
25*4882a593Smuzhiyun * the capabilities register, and the resulting divisor will be
26*4882a593Smuzhiyun * doubled, meaning that the clock control register will be set to the
27*4882a593Smuzhiyun * in-spec 52 MHz value.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun #define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * When the minimum clock frequency is set to 0 (auto-detect), U-Boot
32*4882a593Smuzhiyun * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
33*4882a593Smuzhiyun * which results in the controller timing out when trying to
34*4882a593Smuzhiyun * communicate with the MMC device. Hard-code this value to 400000
35*4882a593Smuzhiyun * (400 kHz) to prevent this.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun #define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * This driver has only been tested with eMMC devices; SD devices may
43*4882a593Smuzhiyun * not work.
44*4882a593Smuzhiyun */
bcmstb_sdhci_init(phys_addr_t regbase)45*4882a593Smuzhiyun int bcmstb_sdhci_init(phys_addr_t regbase)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct sdhci_host *host = NULL;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
50*4882a593Smuzhiyun if (!host) {
51*4882a593Smuzhiyun printf("%s: Failed to allocate memory\n", __func__);
52*4882a593Smuzhiyun return 1;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun memset(host, 0, sizeof(*host));
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun host->name = BCMSTB_SDHCI_NAME;
57*4882a593Smuzhiyun host->ioaddr = (void *)regbase;
58*4882a593Smuzhiyun host->quirks = 0;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun host->cfg.part_type = PART_TYPE_DOS;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return add_sdhci(host,
65*4882a593Smuzhiyun BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
66*4882a593Smuzhiyun BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
67*4882a593Smuzhiyun }
68