1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2019 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <common.h>
6*4882a593Smuzhiyun #include <asm/io.h>
7*4882a593Smuzhiyun #include <clk.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <misc.h>
11*4882a593Smuzhiyun #include <irq-generic.h>
12*4882a593Smuzhiyun #include <reset.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define DECOM_CTRL 0x0
17*4882a593Smuzhiyun #define DECOM_ENR 0x4
18*4882a593Smuzhiyun #define DECOM_RADDR 0x8
19*4882a593Smuzhiyun #define DECOM_WADDR 0xc
20*4882a593Smuzhiyun #define DECOM_UDDSL 0x10
21*4882a593Smuzhiyun #define DECOM_UDDSH 0x14
22*4882a593Smuzhiyun #define DECOM_TXTHR 0x18
23*4882a593Smuzhiyun #define DECOM_RXTHR 0x1c
24*4882a593Smuzhiyun #define DECOM_SLEN 0x20
25*4882a593Smuzhiyun #define DECOM_STAT 0x24
26*4882a593Smuzhiyun #define DECOM_ISR 0x28
27*4882a593Smuzhiyun #define DECOM_IEN 0x2c
28*4882a593Smuzhiyun #define DECOM_AXI_STAT 0x30
29*4882a593Smuzhiyun #define DECOM_TSIZEL 0x34
30*4882a593Smuzhiyun #define DECOM_TSIZEH 0x38
31*4882a593Smuzhiyun #define DECOM_MGNUM 0x3c
32*4882a593Smuzhiyun #define DECOM_FRAME 0x40
33*4882a593Smuzhiyun #define DECOM_DICTID 0x44
34*4882a593Smuzhiyun #define DECOM_CSL 0x48
35*4882a593Smuzhiyun #define DECOM_CSH 0x4c
36*4882a593Smuzhiyun #define DECOM_LMTSL 0x50
37*4882a593Smuzhiyun #define DECOM_LMTSH 0x54
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define LZ4_HEAD_CSUM_CHECK_EN BIT(1)
40*4882a593Smuzhiyun #define LZ4_BLOCK_CSUM_CHECK_EN BIT(2)
41*4882a593Smuzhiyun #define LZ4_CONT_CSUM_CHECK_EN BIT(3)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define DSOLIEN BIT(19)
44*4882a593Smuzhiyun #define ZDICTEIEN BIT(18)
45*4882a593Smuzhiyun #define GCMEIEN BIT(17)
46*4882a593Smuzhiyun #define GIDEIEN BIT(16)
47*4882a593Smuzhiyun #define CCCEIEN BIT(15)
48*4882a593Smuzhiyun #define BCCEIEN BIT(14)
49*4882a593Smuzhiyun #define HCCEIEN BIT(13)
50*4882a593Smuzhiyun #define CSEIEN BIT(12)
51*4882a593Smuzhiyun #define DICTEIEN BIT(11)
52*4882a593Smuzhiyun #define VNEIEN BIT(10)
53*4882a593Smuzhiyun #define WNEIEN BIT(9)
54*4882a593Smuzhiyun #define RDCEIEN BIT(8)
55*4882a593Smuzhiyun #define WRCEIEN BIT(7)
56*4882a593Smuzhiyun #define DISEIEN BIT(6)
57*4882a593Smuzhiyun #define LENEIEN BIT(5)
58*4882a593Smuzhiyun #define LITEIEN BIT(4)
59*4882a593Smuzhiyun #define SQMEIEN BIT(3)
60*4882a593Smuzhiyun #define SLCIEN BIT(2)
61*4882a593Smuzhiyun #define HDEIEN BIT(1)
62*4882a593Smuzhiyun #define DSIEN BIT(0)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define DECOM_STOP BIT(0)
65*4882a593Smuzhiyun #define DECOM_COMPLETE BIT(0)
66*4882a593Smuzhiyun #define DECOM_GZIP_MODE BIT(4)
67*4882a593Smuzhiyun #define DECOM_ZLIB_MODE BIT(5)
68*4882a593Smuzhiyun #define DECOM_DEFLATE_MODE BIT(0)
69*4882a593Smuzhiyun #define DECOM_AXI_IDLE BIT(4)
70*4882a593Smuzhiyun #define DECOM_LZ4_MODE 0
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define DECOM_ENABLE 0x1
73*4882a593Smuzhiyun #define DECOM_DISABLE 0x0
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define DECOM_IRQ 0xffff /* fixme */
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define DECOM_INT_MASK \
78*4882a593Smuzhiyun (DSOLIEN | ZDICTEIEN | GCMEIEN | GIDEIEN | \
79*4882a593Smuzhiyun CCCEIEN | BCCEIEN | HCCEIEN | CSEIEN | \
80*4882a593Smuzhiyun DICTEIEN | VNEIEN | WNEIEN | RDCEIEN | WRCEIEN | \
81*4882a593Smuzhiyun DISEIEN | LENEIEN | LITEIEN | SQMEIEN | SLCIEN | \
82*4882a593Smuzhiyun HDEIEN | DSIEN)
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define DCLK_DECOM 400 * 1000 * 1000
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct rockchip_decom_priv {
87*4882a593Smuzhiyun struct reset_ctl rst;
88*4882a593Smuzhiyun void __iomem *base;
89*4882a593Smuzhiyun bool idle_check_once;
90*4882a593Smuzhiyun bool done;
91*4882a593Smuzhiyun struct clk dclk;
92*4882a593Smuzhiyun int cached; /* 1: access the data through dcache; 0: no dcache */
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
rockchip_decom_start(struct udevice * dev,void * buf)95*4882a593Smuzhiyun static int rockchip_decom_start(struct udevice *dev, void *buf)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
98*4882a593Smuzhiyun struct decom_param *param = (struct decom_param *)buf;
99*4882a593Smuzhiyun unsigned int limit_lo = param->size_dst & 0xffffffff;
100*4882a593Smuzhiyun unsigned int limit_hi = param->size_dst >> 32;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(DM_RESET)
103*4882a593Smuzhiyun reset_assert(&priv->rst);
104*4882a593Smuzhiyun udelay(10);
105*4882a593Smuzhiyun reset_deassert(&priv->rst);
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Purpose:
109*4882a593Smuzhiyun * src: clean dcache to get the real compressed data from ddr.
110*4882a593Smuzhiyun * dst: invalidate dcache.
111*4882a593Smuzhiyun *
112*4882a593Smuzhiyun * flush_dcache_all() operating on set/way is faster than
113*4882a593Smuzhiyun * flush_cache() and invalidate_dcache_range() operating
114*4882a593Smuzhiyun * on virtual address.
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun if (!priv->cached)
117*4882a593Smuzhiyun flush_dcache_all();
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun priv->done = false;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (param->mode == DECOM_LZ4)
122*4882a593Smuzhiyun writel(LZ4_CONT_CSUM_CHECK_EN |
123*4882a593Smuzhiyun LZ4_HEAD_CSUM_CHECK_EN |
124*4882a593Smuzhiyun LZ4_BLOCK_CSUM_CHECK_EN |
125*4882a593Smuzhiyun DECOM_LZ4_MODE,
126*4882a593Smuzhiyun priv->base + DECOM_CTRL);
127*4882a593Smuzhiyun else if (param->mode == DECOM_GZIP)
128*4882a593Smuzhiyun writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE,
129*4882a593Smuzhiyun priv->base + DECOM_CTRL);
130*4882a593Smuzhiyun else if (param->mode == DECOM_ZLIB)
131*4882a593Smuzhiyun writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE,
132*4882a593Smuzhiyun priv->base + DECOM_CTRL);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun writel(param->addr_src, priv->base + DECOM_RADDR);
135*4882a593Smuzhiyun writel(param->addr_dst, priv->base + DECOM_WADDR);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun writel(limit_lo, priv->base + DECOM_LMTSL);
138*4882a593Smuzhiyun writel(limit_hi, priv->base + DECOM_LMTSH);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun writel(DECOM_ENABLE, priv->base + DECOM_ENR);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun priv->idle_check_once = true;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
rockchip_decom_stop(struct udevice * dev)147*4882a593Smuzhiyun static int rockchip_decom_stop(struct udevice *dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun writel(DECOM_DISABLE, priv->base + DECOM_ENR);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Caller must call this function to check if decompress done */
rockchip_decom_done_poll(struct udevice * dev)157*4882a593Smuzhiyun static int rockchip_decom_done_poll(struct udevice *dev)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /*
162*4882a593Smuzhiyun * Test the decom is idle first time.
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun if (!priv->idle_check_once)
165*4882a593Smuzhiyun return !(readl(priv->base + DECOM_AXI_STAT) & DECOM_AXI_IDLE);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return !(readl(priv->base + DECOM_STAT) & DECOM_COMPLETE);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
rockchip_decom_capability(u32 * buf)170*4882a593Smuzhiyun static int rockchip_decom_capability(u32 *buf)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun *buf = DECOM_GZIP | DECOM_LZ4;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
rockchip_decom_data_size(struct udevice * dev,u64 * buf)177*4882a593Smuzhiyun static int rockchip_decom_data_size(struct udevice *dev, u64 *buf)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
180*4882a593Smuzhiyun struct decom_param *param = (struct decom_param *)buf;
181*4882a593Smuzhiyun u32 sizel, sizeh;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun sizel = readl(priv->base + DECOM_TSIZEL);
184*4882a593Smuzhiyun sizeh = readl(priv->base + DECOM_TSIZEH);
185*4882a593Smuzhiyun param->size_dst = sizel | ((u64)sizeh << 32);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* Caller must fill in param @buf which represent struct decom_param */
rockchip_decom_ioctl(struct udevice * dev,unsigned long request,void * buf)191*4882a593Smuzhiyun static int rockchip_decom_ioctl(struct udevice *dev, unsigned long request,
192*4882a593Smuzhiyun void *buf)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun int ret = -EINVAL;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun switch (request) {
197*4882a593Smuzhiyun case IOCTL_REQ_START:
198*4882a593Smuzhiyun ret = rockchip_decom_start(dev, buf);
199*4882a593Smuzhiyun break;
200*4882a593Smuzhiyun case IOCTL_REQ_POLL:
201*4882a593Smuzhiyun ret = rockchip_decom_done_poll(dev);
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun case IOCTL_REQ_STOP:
204*4882a593Smuzhiyun ret = rockchip_decom_stop(dev);
205*4882a593Smuzhiyun break;
206*4882a593Smuzhiyun case IOCTL_REQ_CAPABILITY:
207*4882a593Smuzhiyun ret = rockchip_decom_capability(buf);
208*4882a593Smuzhiyun break;
209*4882a593Smuzhiyun case IOCTL_REQ_DATA_SIZE:
210*4882a593Smuzhiyun ret = rockchip_decom_data_size(dev, buf);
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun default:
213*4882a593Smuzhiyun printf("Unsupported ioctl: %ld\n", (ulong)request);
214*4882a593Smuzhiyun break;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun static const struct misc_ops rockchip_decom_ops = {
221*4882a593Smuzhiyun .ioctl = rockchip_decom_ioctl,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
rockchip_decom_ofdata_to_platdata(struct udevice * dev)224*4882a593Smuzhiyun static int rockchip_decom_ofdata_to_platdata(struct udevice *dev)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun priv->base = dev_read_addr_ptr(dev);
229*4882a593Smuzhiyun if (!priv->base)
230*4882a593Smuzhiyun return -ENOENT;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun priv->cached = dev_read_u32_default(dev, "data-cached", 0);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
rockchip_decom_probe(struct udevice * dev)237*4882a593Smuzhiyun static int rockchip_decom_probe(struct udevice *dev)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct rockchip_decom_priv *priv = dev_get_priv(dev);
240*4882a593Smuzhiyun int ret;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(DM_RESET)
243*4882a593Smuzhiyun ret = reset_get_by_name(dev, "dresetn", &priv->rst);
244*4882a593Smuzhiyun if (ret) {
245*4882a593Smuzhiyun debug("reset_get_by_name() failed: %d\n", ret);
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun #endif
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun ret = clk_get_by_index(dev, 1, &priv->dclk);
251*4882a593Smuzhiyun if (ret < 0)
252*4882a593Smuzhiyun return ret;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ret = clk_set_rate(&priv->dclk, DCLK_DECOM);
255*4882a593Smuzhiyun if (ret < 0)
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return 0;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun static const struct udevice_id rockchip_decom_ids[] = {
262*4882a593Smuzhiyun { .compatible = "rockchip,hw-decompress" },
263*4882a593Smuzhiyun {}
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun U_BOOT_DRIVER(rockchip_hw_decompress) = {
267*4882a593Smuzhiyun .name = "rockchip_hw_decompress",
268*4882a593Smuzhiyun .id = UCLASS_MISC,
269*4882a593Smuzhiyun .of_match = rockchip_decom_ids,
270*4882a593Smuzhiyun .probe = rockchip_decom_probe,
271*4882a593Smuzhiyun .ofdata_to_platdata = rockchip_decom_ofdata_to_platdata,
272*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rockchip_decom_priv),
273*4882a593Smuzhiyun .ops = &rockchip_decom_ops,
274*4882a593Smuzhiyun };
275