1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Extreme Engineering Solutions, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DS4510_H_ 8*4882a593Smuzhiyun #define __DS4510_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* General defines */ 11*4882a593Smuzhiyun #define DS4510_NUM_IO 0x04 12*4882a593Smuzhiyun #define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) 13*4882a593Smuzhiyun #define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* EEPROM from 0x00 - 0x39 */ 16*4882a593Smuzhiyun #define DS4510_EEPROM 0x00 17*4882a593Smuzhiyun #define DS4510_EEPROM_SIZE 0x40 18*4882a593Smuzhiyun #define DS4510_EEPROM_PAGE_SIZE 0x08 19*4882a593Smuzhiyun #define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SEEPROM from 0xf0 - 0xf7 */ 22*4882a593Smuzhiyun #define DS4510_SEEPROM 0xf0 23*4882a593Smuzhiyun #define DS4510_SEEPROM_SIZE 0x08 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ 26*4882a593Smuzhiyun #define DS4510_PULLUP 0xF0 27*4882a593Smuzhiyun #define DS4510_PULLUP_DIS 0x00 28*4882a593Smuzhiyun #define DS4510_PULLUP_EN 0x01 29*4882a593Smuzhiyun #define DS4510_RSTDELAY 0xF1 30*4882a593Smuzhiyun #define DS4510_RSTDELAY_MASK 0x03 31*4882a593Smuzhiyun #define DS4510_RSTDELAY_125 0x00 32*4882a593Smuzhiyun #define DS4510_RSTDELAY_250 0x01 33*4882a593Smuzhiyun #define DS4510_RSTDELAY_500 0x02 34*4882a593Smuzhiyun #define DS4510_RSTDELAY_1000 0x03 35*4882a593Smuzhiyun #define DS4510_IO3 0xF4 36*4882a593Smuzhiyun #define DS4510_IO2 0xF5 37*4882a593Smuzhiyun #define DS4510_IO1 0xF6 38*4882a593Smuzhiyun #define DS4510_IO0 0xF7 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Status configuration registers from 0xf8 - 0xf9*/ 41*4882a593Smuzhiyun #define DS4510_IO_STATUS 0xF8 42*4882a593Smuzhiyun #define DS4510_CFG 0xF9 43*4882a593Smuzhiyun #define DS4510_CFG_READY 0x80 44*4882a593Smuzhiyun #define DS4510_CFG_TRIP_POINT 0x40 45*4882a593Smuzhiyun #define DS4510_CFG_RESET 0x20 46*4882a593Smuzhiyun #define DS4510_CFG_SEE 0x10 47*4882a593Smuzhiyun #define DS4510_CFG_SWRST 0x08 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* SRAM from 0xfa - 0xff */ 50*4882a593Smuzhiyun #define DS4510_SRAM 0xfa 51*4882a593Smuzhiyun #define DS4510_SRAM_SIZE 0x06 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* __DS4510_H_ */ 54