xref: /OK3568_Linux_fs/u-boot/drivers/misc/ds4510.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2008 Extreme Engineering Solutions, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun  * Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM,
9*4882a593Smuzhiyun  * and 4 programmable non-volatile GPIO pins.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include <command.h>
15*4882a593Smuzhiyun #include "ds4510.h"
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun enum {
18*4882a593Smuzhiyun 	DS4510_CMD_INFO,
19*4882a593Smuzhiyun 	DS4510_CMD_DEVICE,
20*4882a593Smuzhiyun 	DS4510_CMD_NV,
21*4882a593Smuzhiyun 	DS4510_CMD_RSTDELAY,
22*4882a593Smuzhiyun 	DS4510_CMD_OUTPUT,
23*4882a593Smuzhiyun 	DS4510_CMD_INPUT,
24*4882a593Smuzhiyun 	DS4510_CMD_PULLUP,
25*4882a593Smuzhiyun 	DS4510_CMD_EEPROM,
26*4882a593Smuzhiyun 	DS4510_CMD_SEEPROM,
27*4882a593Smuzhiyun 	DS4510_CMD_SRAM,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * Write to DS4510, taking page boundaries into account
32*4882a593Smuzhiyun  */
ds4510_mem_write(uint8_t chip,int offset,uint8_t * buf,int count)33*4882a593Smuzhiyun static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	int wrlen;
36*4882a593Smuzhiyun 	int i = 0;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	do {
39*4882a593Smuzhiyun 		wrlen = DS4510_EEPROM_PAGE_SIZE -
40*4882a593Smuzhiyun 			DS4510_EEPROM_PAGE_OFFSET(offset);
41*4882a593Smuzhiyun 		if (count < wrlen)
42*4882a593Smuzhiyun 			wrlen = count;
43*4882a593Smuzhiyun 		if (i2c_write(chip, offset, 1, &buf[i], wrlen))
44*4882a593Smuzhiyun 			return -1;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 		/*
47*4882a593Smuzhiyun 		 * This delay isn't needed for SRAM writes but shouldn't delay
48*4882a593Smuzhiyun 		 * things too much, so do it unconditionally for simplicity
49*4882a593Smuzhiyun 		 */
50*4882a593Smuzhiyun 		udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
51*4882a593Smuzhiyun 		count -= wrlen;
52*4882a593Smuzhiyun 		offset += wrlen;
53*4882a593Smuzhiyun 		i += wrlen;
54*4882a593Smuzhiyun 	} while (count > 0);
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun  * General read from DS4510
61*4882a593Smuzhiyun  */
ds4510_mem_read(uint8_t chip,int offset,uint8_t * buf,int count)62*4882a593Smuzhiyun static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	return i2c_read(chip, offset, 1, buf, count);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * Write SEE bit in config register.
69*4882a593Smuzhiyun  * nv = 0 - Writes to SEEPROM registers behave like EEPROM
70*4882a593Smuzhiyun  * nv = 1 - Writes to SEEPROM registers behave like SRAM
71*4882a593Smuzhiyun  */
ds4510_see_write(uint8_t chip,uint8_t nv)72*4882a593Smuzhiyun static int ds4510_see_write(uint8_t chip, uint8_t nv)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	uint8_t data;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
77*4882a593Smuzhiyun 		return -1;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	if (nv)	/* Treat SEEPROM bits as EEPROM */
80*4882a593Smuzhiyun 		data &= ~DS4510_CFG_SEE;
81*4882a593Smuzhiyun 	else	/* Treat SEEPROM bits as SRAM */
82*4882a593Smuzhiyun 		data |= DS4510_CFG_SEE;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	return ds4510_mem_write(chip, DS4510_CFG, &data, 1);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun  * Write de-assertion of reset signal delay
89*4882a593Smuzhiyun  */
ds4510_rstdelay_write(uint8_t chip,uint8_t delay)90*4882a593Smuzhiyun static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	uint8_t data;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
95*4882a593Smuzhiyun 		return -1;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	data &= ~DS4510_RSTDELAY_MASK;
98*4882a593Smuzhiyun 	data |= delay & DS4510_RSTDELAY_MASK;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * Write pullup characteristics of IO pins
105*4882a593Smuzhiyun  */
ds4510_pullup_write(uint8_t chip,uint8_t val)106*4882a593Smuzhiyun static int ds4510_pullup_write(uint8_t chip, uint8_t val)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	val &= DS4510_IO_MASK;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun  * Read pullup characteristics of IO pins
115*4882a593Smuzhiyun  */
ds4510_pullup_read(uint8_t chip)116*4882a593Smuzhiyun static int ds4510_pullup_read(uint8_t chip)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	uint8_t val;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1))
121*4882a593Smuzhiyun 		return -1;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return val & DS4510_IO_MASK;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /*
127*4882a593Smuzhiyun  * Write drive level of IO pins
128*4882a593Smuzhiyun  */
ds4510_gpio_write(uint8_t chip,uint8_t val)129*4882a593Smuzhiyun static int ds4510_gpio_write(uint8_t chip, uint8_t val)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	uint8_t data;
132*4882a593Smuzhiyun 	int i;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	for (i = 0; i < DS4510_NUM_IO; i++) {
135*4882a593Smuzhiyun 		if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
136*4882a593Smuzhiyun 			return -1;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 		if (val & (0x1 << i))
139*4882a593Smuzhiyun 			data |= 0x1;
140*4882a593Smuzhiyun 		else
141*4882a593Smuzhiyun 			data &= ~0x1;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 		if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1))
144*4882a593Smuzhiyun 			return -1;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun  * Read drive level of IO pins
152*4882a593Smuzhiyun  */
ds4510_gpio_read(uint8_t chip)153*4882a593Smuzhiyun static int ds4510_gpio_read(uint8_t chip)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	uint8_t data;
156*4882a593Smuzhiyun 	int val = 0;
157*4882a593Smuzhiyun 	int i;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	for (i = 0; i < DS4510_NUM_IO; i++) {
160*4882a593Smuzhiyun 		if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
161*4882a593Smuzhiyun 			return -1;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 		if (data & 1)
164*4882a593Smuzhiyun 			val |= (1 << i);
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return val;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun  * Read physical level of IO pins
172*4882a593Smuzhiyun  */
ds4510_gpio_read_val(uint8_t chip)173*4882a593Smuzhiyun static int ds4510_gpio_read_val(uint8_t chip)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	uint8_t val;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1))
178*4882a593Smuzhiyun 		return -1;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	return val & DS4510_IO_MASK;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /*
184*4882a593Smuzhiyun  * Display DS4510 information
185*4882a593Smuzhiyun  */
ds4510_info(uint8_t chip)186*4882a593Smuzhiyun static int ds4510_info(uint8_t chip)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	int i;
189*4882a593Smuzhiyun 	int tmp;
190*4882a593Smuzhiyun 	uint8_t data;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	printf("DS4510 @ 0x%x:\n\n", chip);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
195*4882a593Smuzhiyun 		return -1;
196*4882a593Smuzhiyun 	printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
199*4882a593Smuzhiyun 		return -1;
200*4882a593Smuzhiyun 	printf("config   = 0x%x\n", data);
201*4882a593Smuzhiyun 	printf(" /ready  = %d\n", data & DS4510_CFG_READY ? 1 : 0);
202*4882a593Smuzhiyun 	printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0);
203*4882a593Smuzhiyun 	printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0);
204*4882a593Smuzhiyun 	printf(" /see    = %d\n", data & DS4510_CFG_SEE ? 1 : 0);
205*4882a593Smuzhiyun 	printf(" swrst   = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	printf("gpio pins: 3210\n");
208*4882a593Smuzhiyun 	printf("---------------\n");
209*4882a593Smuzhiyun 	printf("pullup     ");
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	tmp = ds4510_pullup_read(chip);
212*4882a593Smuzhiyun 	if (tmp == -1)
213*4882a593Smuzhiyun 		return tmp;
214*4882a593Smuzhiyun 	for (i = DS4510_NUM_IO - 1; i >= 0; i--)
215*4882a593Smuzhiyun 		printf("%d", (tmp & (1 << i)) ? 1 : 0);
216*4882a593Smuzhiyun 	printf("\n");
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	printf("driven     ");
219*4882a593Smuzhiyun 	tmp = ds4510_gpio_read(chip);
220*4882a593Smuzhiyun 	if (tmp == -1)
221*4882a593Smuzhiyun 		return -1;
222*4882a593Smuzhiyun 	for (i = DS4510_NUM_IO - 1; i >= 0; i--)
223*4882a593Smuzhiyun 		printf("%d", (tmp & (1 << i)) ? 1 : 0);
224*4882a593Smuzhiyun 	printf("\n");
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	printf("read       ");
227*4882a593Smuzhiyun 	tmp = ds4510_gpio_read_val(chip);
228*4882a593Smuzhiyun 	if (tmp == -1)
229*4882a593Smuzhiyun 		return -1;
230*4882a593Smuzhiyun 	for (i = DS4510_NUM_IO - 1; i >= 0; i--)
231*4882a593Smuzhiyun 		printf("%d", (tmp & (1 << i)) ? 1 : 0);
232*4882a593Smuzhiyun 	printf("\n");
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun cmd_tbl_t cmd_ds4510[] = {
238*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""),
239*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""),
240*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""),
241*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""),
242*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""),
243*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""),
244*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""),
245*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""),
246*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""),
247*4882a593Smuzhiyun 	U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""),
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun 
do_ds4510(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])250*4882a593Smuzhiyun int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	static uint8_t chip = 0x51;
253*4882a593Smuzhiyun 	cmd_tbl_t *c;
254*4882a593Smuzhiyun 	ulong ul_arg2 = 0;
255*4882a593Smuzhiyun 	ulong ul_arg3 = 0;
256*4882a593Smuzhiyun 	int tmp;
257*4882a593Smuzhiyun 	ulong addr;
258*4882a593Smuzhiyun 	ulong off;
259*4882a593Smuzhiyun 	ulong cnt;
260*4882a593Smuzhiyun 	int end;
261*4882a593Smuzhiyun 	int (*rw_func)(uint8_t, int, uint8_t *, int);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510));
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	/* All commands but "device" require 'maxargs' arguments */
266*4882a593Smuzhiyun 	if (!c || !((argc == (c->maxargs)) ||
267*4882a593Smuzhiyun 		(((int)c->cmd == DS4510_CMD_DEVICE) &&
268*4882a593Smuzhiyun 		 (argc == (c->maxargs - 1))))) {
269*4882a593Smuzhiyun 		return cmd_usage(cmdtp);
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* arg2 used as chip addr and pin number */
273*4882a593Smuzhiyun 	if (argc > 2)
274*4882a593Smuzhiyun 		ul_arg2 = simple_strtoul(argv[2], NULL, 16);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	/* arg3 used as output/pullup value */
277*4882a593Smuzhiyun 	if (argc > 3)
278*4882a593Smuzhiyun 		ul_arg3 = simple_strtoul(argv[3], NULL, 16);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	switch ((int)c->cmd) {
281*4882a593Smuzhiyun 	case DS4510_CMD_DEVICE:
282*4882a593Smuzhiyun 		if (argc == 3)
283*4882a593Smuzhiyun 			chip = ul_arg2;
284*4882a593Smuzhiyun 		printf("Current device address: 0x%x\n", chip);
285*4882a593Smuzhiyun 		return 0;
286*4882a593Smuzhiyun 	case DS4510_CMD_NV:
287*4882a593Smuzhiyun 		return ds4510_see_write(chip, ul_arg2);
288*4882a593Smuzhiyun 	case DS4510_CMD_OUTPUT:
289*4882a593Smuzhiyun 		tmp = ds4510_gpio_read(chip);
290*4882a593Smuzhiyun 		if (tmp == -1)
291*4882a593Smuzhiyun 			return -1;
292*4882a593Smuzhiyun 		if (ul_arg3)
293*4882a593Smuzhiyun 			tmp |= (1 << ul_arg2);
294*4882a593Smuzhiyun 		else
295*4882a593Smuzhiyun 			tmp &= ~(1 << ul_arg2);
296*4882a593Smuzhiyun 		return ds4510_gpio_write(chip, tmp);
297*4882a593Smuzhiyun 	case DS4510_CMD_INPUT:
298*4882a593Smuzhiyun 		tmp = ds4510_gpio_read_val(chip);
299*4882a593Smuzhiyun 		if (tmp == -1)
300*4882a593Smuzhiyun 			return -1;
301*4882a593Smuzhiyun 		return (tmp & (1 << ul_arg2)) != 0;
302*4882a593Smuzhiyun 	case DS4510_CMD_PULLUP:
303*4882a593Smuzhiyun 		tmp = ds4510_pullup_read(chip);
304*4882a593Smuzhiyun 		if (tmp == -1)
305*4882a593Smuzhiyun 			return -1;
306*4882a593Smuzhiyun 		if (ul_arg3)
307*4882a593Smuzhiyun 			tmp |= (1 << ul_arg2);
308*4882a593Smuzhiyun 		else
309*4882a593Smuzhiyun 			tmp &= ~(1 << ul_arg2);
310*4882a593Smuzhiyun 		return ds4510_pullup_write(chip, tmp);
311*4882a593Smuzhiyun 	case DS4510_CMD_INFO:
312*4882a593Smuzhiyun 		return ds4510_info(chip);
313*4882a593Smuzhiyun 	case DS4510_CMD_RSTDELAY:
314*4882a593Smuzhiyun 		return ds4510_rstdelay_write(chip, ul_arg2);
315*4882a593Smuzhiyun 	case DS4510_CMD_EEPROM:
316*4882a593Smuzhiyun 		end = DS4510_EEPROM + DS4510_EEPROM_SIZE;
317*4882a593Smuzhiyun 		off = DS4510_EEPROM;
318*4882a593Smuzhiyun 		break;
319*4882a593Smuzhiyun 	case DS4510_CMD_SEEPROM:
320*4882a593Smuzhiyun 		end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE;
321*4882a593Smuzhiyun 		off = DS4510_SEEPROM;
322*4882a593Smuzhiyun 		break;
323*4882a593Smuzhiyun 	case DS4510_CMD_SRAM:
324*4882a593Smuzhiyun 		end = DS4510_SRAM + DS4510_SRAM_SIZE;
325*4882a593Smuzhiyun 		off = DS4510_SRAM;
326*4882a593Smuzhiyun 		break;
327*4882a593Smuzhiyun 	default:
328*4882a593Smuzhiyun 		/* We should never get here... */
329*4882a593Smuzhiyun 		return 1;
330*4882a593Smuzhiyun 	}
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	/* Only eeprom, seeprom, and sram commands should make it here */
333*4882a593Smuzhiyun 	if (strcmp(argv[2], "read") == 0)
334*4882a593Smuzhiyun 		rw_func = ds4510_mem_read;
335*4882a593Smuzhiyun 	else if (strcmp(argv[2], "write") == 0)
336*4882a593Smuzhiyun 		rw_func = ds4510_mem_write;
337*4882a593Smuzhiyun 	else
338*4882a593Smuzhiyun 		return cmd_usage(cmdtp);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	addr = simple_strtoul(argv[3], NULL, 16);
341*4882a593Smuzhiyun 	off += simple_strtoul(argv[4], NULL, 16);
342*4882a593Smuzhiyun 	cnt = simple_strtoul(argv[5], NULL, 16);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	if ((off + cnt) > end) {
345*4882a593Smuzhiyun 		printf("ERROR: invalid len\n");
346*4882a593Smuzhiyun 		return -1;
347*4882a593Smuzhiyun 	}
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	return rw_func(chip, off, (uint8_t *)addr, cnt);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun U_BOOT_CMD(
353*4882a593Smuzhiyun 	ds4510,	6,	1,	do_ds4510,
354*4882a593Smuzhiyun 	"ds4510 eeprom/seeprom/sram/gpio access",
355*4882a593Smuzhiyun 	"device [dev]\n"
356*4882a593Smuzhiyun 	"	- show or set current device address\n"
357*4882a593Smuzhiyun 	"ds4510 info\n"
358*4882a593Smuzhiyun 	"	- display ds4510 info\n"
359*4882a593Smuzhiyun 	"ds4510 output pin 0|1\n"
360*4882a593Smuzhiyun 	"	- set pin low or high-Z\n"
361*4882a593Smuzhiyun 	"ds4510 input pin\n"
362*4882a593Smuzhiyun 	"	- read value of pin\n"
363*4882a593Smuzhiyun 	"ds4510 pullup pin 0|1\n"
364*4882a593Smuzhiyun 	"	- disable/enable pullup on specified pin\n"
365*4882a593Smuzhiyun 	"ds4510 nv 0|1\n"
366*4882a593Smuzhiyun 	"	- make gpio and seeprom writes volatile/non-volatile"
367*4882a593Smuzhiyun 	"\n"
368*4882a593Smuzhiyun 	"ds4510 rstdelay 0-3\n"
369*4882a593Smuzhiyun 	"	- set reset output delay"
370*4882a593Smuzhiyun 	"\n"
371*4882a593Smuzhiyun 	"ds4510 eeprom read addr off cnt\n"
372*4882a593Smuzhiyun 	"ds4510 eeprom write addr off cnt\n"
373*4882a593Smuzhiyun 	"	- read/write 'cnt' bytes at EEPROM offset 'off'\n"
374*4882a593Smuzhiyun 	"ds4510 seeprom read addr off cnt\n"
375*4882a593Smuzhiyun 	"ds4510 seeprom write addr off cnt\n"
376*4882a593Smuzhiyun 	"	- read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n"
377*4882a593Smuzhiyun 	"ds4510 sram read addr off cnt\n"
378*4882a593Smuzhiyun 	"ds4510 sram write addr off cnt\n"
379*4882a593Smuzhiyun 	"	- read/write 'cnt' bytes at SRAM offset 'off'"
380*4882a593Smuzhiyun );
381