1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Keystone2: Asynchronous EMIF Configuration
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2012-2014
5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/ti-common/ti-aemif.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4)
14*4882a593Smuzhiyun #define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60)
15*4882a593Smuzhiyun #define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c)
16*4882a593Smuzhiyun #define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \
17*4882a593Smuzhiyun + (cs * 4))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
20*4882a593Smuzhiyun #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
21*4882a593Smuzhiyun #define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
22*4882a593Smuzhiyun #define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
23*4882a593Smuzhiyun #define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
24*4882a593Smuzhiyun #define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
25*4882a593Smuzhiyun #define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
26*4882a593Smuzhiyun #define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
27*4882a593Smuzhiyun #define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
28*4882a593Smuzhiyun #define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define set_config_field(reg, field, val) \
31*4882a593Smuzhiyun do { \
32*4882a593Smuzhiyun if (val != -1) { \
33*4882a593Smuzhiyun reg &= ~AEMIF_CFG_##field(0xffffffff); \
34*4882a593Smuzhiyun reg |= AEMIF_CFG_##field(val); \
35*4882a593Smuzhiyun } \
36*4882a593Smuzhiyun } while (0)
37*4882a593Smuzhiyun
aemif_configure(int cs,struct aemif_config * cfg)38*4882a593Smuzhiyun static void aemif_configure(int cs, struct aemif_config *cfg)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun unsigned long tmp;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (cfg->mode == AEMIF_MODE_NAND) {
43*4882a593Smuzhiyun tmp = __raw_readl(AEMIF_NAND_CONTROL);
44*4882a593Smuzhiyun tmp |= (1 << cs);
45*4882a593Smuzhiyun __raw_writel(tmp, AEMIF_NAND_CONTROL);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun } else if (cfg->mode == AEMIF_MODE_ONENAND) {
48*4882a593Smuzhiyun tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
49*4882a593Smuzhiyun tmp |= (1 << cs);
50*4882a593Smuzhiyun __raw_writel(tmp, AEMIF_ONENAND_CONTROL);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun tmp = __raw_readl(AEMIF_CONFIG(cs));
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
56*4882a593Smuzhiyun set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
57*4882a593Smuzhiyun set_config_field(tmp, WR_SETUP, cfg->wr_setup);
58*4882a593Smuzhiyun set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
59*4882a593Smuzhiyun set_config_field(tmp, WR_HOLD, cfg->wr_hold);
60*4882a593Smuzhiyun set_config_field(tmp, RD_SETUP, cfg->rd_setup);
61*4882a593Smuzhiyun set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
62*4882a593Smuzhiyun set_config_field(tmp, RD_HOLD, cfg->rd_hold);
63*4882a593Smuzhiyun set_config_field(tmp, TURN_AROUND, cfg->turn_around);
64*4882a593Smuzhiyun set_config_field(tmp, WIDTH, cfg->width);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun __raw_writel(tmp, AEMIF_CONFIG(cs));
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
aemif_init(int num_cs,struct aemif_config * config)69*4882a593Smuzhiyun void aemif_init(int num_cs, struct aemif_config *config)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int cs;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (num_cs > AEMIF_NUM_CS) {
74*4882a593Smuzhiyun num_cs = AEMIF_NUM_CS;
75*4882a593Smuzhiyun printf("AEMIF: csnum has to be <= 5");
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun for (cs = 0; cs < num_cs; cs++)
79*4882a593Smuzhiyun aemif_configure(cs, config + cs);
80*4882a593Smuzhiyun }
81