1*4882a593Smuzhiyunmenu "Mailbox Controller Support" 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig DM_MAILBOX 4*4882a593Smuzhiyun bool "Enable mailbox controllers using Driver Model" 5*4882a593Smuzhiyun depends on DM && OF_CONTROL 6*4882a593Smuzhiyun help 7*4882a593Smuzhiyun Enable support for the mailbox driver class. Mailboxes provide the 8*4882a593Smuzhiyun ability to transfer small messages and/or notifications from one 9*4882a593Smuzhiyun CPU to another CPU, or sometimes to dedicated HW modules. They form 10*4882a593Smuzhiyun the basis of a variety of inter-process/inter-CPU communication 11*4882a593Smuzhiyun protocols. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunconfig SANDBOX_MBOX 14*4882a593Smuzhiyun bool "Enable the sandbox mailbox test driver" 15*4882a593Smuzhiyun depends on DM_MAILBOX && SANDBOX 16*4882a593Smuzhiyun help 17*4882a593Smuzhiyun Enable support for a test mailbox implementation, which simply echos 18*4882a593Smuzhiyun back a modified version of any message that is sent. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunconfig TEGRA_HSP 21*4882a593Smuzhiyun bool "Enable Tegra HSP controller support" 22*4882a593Smuzhiyun depends on DM_MAILBOX && TEGRA 23*4882a593Smuzhiyun help 24*4882a593Smuzhiyun This enables support for the NVIDIA Tegra HSP Hw module, which 25*4882a593Smuzhiyun implements doorbells, mailboxes, semaphores, and shared interrupts. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunendmenu 28