1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _IRQ_GIC_H_ 8*4882a593Smuzhiyun #define _IRQ_GIC_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/io.h> 11*4882a593Smuzhiyun #include <irq-generic.h> 12*4882a593Smuzhiyun #include <irq-platform.h> 13*4882a593Smuzhiyun #include "irq-internal.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * IRQ FLAG 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define IRQ_FLG_ENABLE BIT(0) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * IRQ-NUMBERS 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define PLATFORM_SUSPEND_MAX_IRQ 12 24*4882a593Smuzhiyun #define PLATFORM_GIC_MAX_IRQ (GIC_IRQS_NR) 25*4882a593Smuzhiyun #define PLATFORM_GPIO_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR) 26*4882a593Smuzhiyun #define PLATFORM_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * IRQ-CHIP 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun struct irq_chip *arch_gic_get_irqchip(void); 32*4882a593Smuzhiyun struct irq_chip *arch_gpio_get_irqchip(void); 33*4882a593Smuzhiyun struct irq_chip *arch_virq_get_irqchip(void); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * IRQ-VIRTUAL 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun int bad_virq(int irq); 39*4882a593Smuzhiyun void virqs_show(int pirq); 40*4882a593Smuzhiyun void virq_free_handler(int irq); 41*4882a593Smuzhiyun int virq_install_handler(int irq, interrupt_handler_t *handler, void *data); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Other 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun int bad_irq(int irq); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * IRQ-GPIO-SWITCH 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define GPIO_BANK_MASK 0xFFFFFF00 52*4882a593Smuzhiyun #define GPIO_BANK_OFFSET 8 53*4882a593Smuzhiyun #define GPIO_PIN_MASK 0x000000FF 54*4882a593Smuzhiyun #define GPIO_PIN_OFFSET 0 55*4882a593Smuzhiyun #define EINVAL_GPIO -1 56*4882a593Smuzhiyun #define PIN_BASE GIC_IRQS_NR 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct gpio_bank { 59*4882a593Smuzhiyun char *name; 60*4882a593Smuzhiyun void __iomem *regbase; 61*4882a593Smuzhiyun int id; 62*4882a593Smuzhiyun int irq_base; 63*4882a593Smuzhiyun int ngpio; 64*4882a593Smuzhiyun int use_count; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define GPIO_BANK_REGISTER(ID, GPIO_BANK_NUM) \ 68*4882a593Smuzhiyun { \ 69*4882a593Smuzhiyun .name = __stringify(gpio##ID), \ 70*4882a593Smuzhiyun .regbase = (unsigned char __iomem *)GPIO##ID##_PHYS, \ 71*4882a593Smuzhiyun .id = ID, \ 72*4882a593Smuzhiyun .irq_base = PIN_BASE + (ID) * (GPIO_BANK_NUM), \ 73*4882a593Smuzhiyun .ngpio = GPIO_BANK_NUM, \ 74*4882a593Smuzhiyun .use_count = 0 \ 75*4882a593Smuzhiyun } 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* gpio bank[31:8] and pin[7:0] */ 78*4882a593Smuzhiyun #define GPIO_BANK(gpio) ((gpio & GPIO_BANK_MASK) >> GPIO_BANK_OFFSET) 79*4882a593Smuzhiyun #define GPIO_PIN(gpio) ((gpio & GPIO_PIN_MASK) >> GPIO_PIN_OFFSET) 80*4882a593Smuzhiyun #define GPIO_BANK_VALID(gpio) (GPIO_BANK(gpio) < GPIO_BANK_NUM) 81*4882a593Smuzhiyun #define GPIO_PIN_VALID(gpio) (GPIO_PIN(gpio) < GPIO_BANK_PINS) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun int hard_gpio_to_irq(u32 gpio); 84*4882a593Smuzhiyun int irq_to_gpio(int irq); 85*4882a593Smuzhiyun struct gpio_bank *gpio_id_to_bank(unsigned int id); 86*4882a593Smuzhiyun struct gpio_bank *gpio_to_bank(unsigned gpio); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun void __generic_gpio_handle_irq(int irq); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* _IRQ_GIC_H_ */ 91