1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _S3C24X0_I2C_H 8*4882a593Smuzhiyun #define _S3C24X0_I2C_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct s3c24x0_i2c { 11*4882a593Smuzhiyun u32 iiccon; 12*4882a593Smuzhiyun u32 iicstat; 13*4882a593Smuzhiyun u32 iicadd; 14*4882a593Smuzhiyun u32 iicds; 15*4882a593Smuzhiyun u32 iiclc; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct exynos5_hsi2c { 19*4882a593Smuzhiyun u32 usi_ctl; 20*4882a593Smuzhiyun u32 usi_fifo_ctl; 21*4882a593Smuzhiyun u32 usi_trailing_ctl; 22*4882a593Smuzhiyun u32 usi_clk_ctl; 23*4882a593Smuzhiyun u32 usi_clk_slot; 24*4882a593Smuzhiyun u32 spi_ctl; 25*4882a593Smuzhiyun u32 uart_ctl; 26*4882a593Smuzhiyun u32 res1; 27*4882a593Smuzhiyun u32 usi_int_en; 28*4882a593Smuzhiyun u32 usi_int_stat; 29*4882a593Smuzhiyun u32 usi_modem_stat; 30*4882a593Smuzhiyun u32 usi_error_stat; 31*4882a593Smuzhiyun u32 usi_fifo_stat; 32*4882a593Smuzhiyun u32 usi_txdata; 33*4882a593Smuzhiyun u32 usi_rxdata; 34*4882a593Smuzhiyun u32 res2; 35*4882a593Smuzhiyun u32 usi_conf; 36*4882a593Smuzhiyun u32 usi_auto_conf; 37*4882a593Smuzhiyun u32 usi_timeout; 38*4882a593Smuzhiyun u32 usi_manual_cmd; 39*4882a593Smuzhiyun u32 usi_trans_status; 40*4882a593Smuzhiyun u32 usi_timing_hs1; 41*4882a593Smuzhiyun u32 usi_timing_hs2; 42*4882a593Smuzhiyun u32 usi_timing_hs3; 43*4882a593Smuzhiyun u32 usi_timing_fs1; 44*4882a593Smuzhiyun u32 usi_timing_fs2; 45*4882a593Smuzhiyun u32 usi_timing_fs3; 46*4882a593Smuzhiyun u32 usi_timing_sla; 47*4882a593Smuzhiyun u32 i2c_addr; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct s3c24x0_i2c_bus { 51*4882a593Smuzhiyun bool active; /* port is active and available */ 52*4882a593Smuzhiyun int node; /* device tree node */ 53*4882a593Smuzhiyun int bus_num; /* i2c bus number */ 54*4882a593Smuzhiyun struct s3c24x0_i2c *regs; 55*4882a593Smuzhiyun struct exynos5_hsi2c *hsregs; 56*4882a593Smuzhiyun int is_highspeed; /* High speed type, rather than I2C */ 57*4882a593Smuzhiyun unsigned clock_frequency; 58*4882a593Smuzhiyun int id; 59*4882a593Smuzhiyun unsigned clk_cycle; 60*4882a593Smuzhiyun unsigned clk_div; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define I2C_WRITE 0 64*4882a593Smuzhiyun #define I2C_READ 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define I2C_OK 0 67*4882a593Smuzhiyun #define I2C_NOK 1 68*4882a593Smuzhiyun #define I2C_NACK 2 69*4882a593Smuzhiyun #define I2C_NOK_LA 3 /* Lost arbitration */ 70*4882a593Smuzhiyun #define I2C_NOK_TOUT 4 /* time out */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* S3C I2C Controller bits */ 73*4882a593Smuzhiyun #define I2CSTAT_BSY 0x20 /* Busy bit */ 74*4882a593Smuzhiyun #define I2CSTAT_NACK 0x01 /* Nack bit */ 75*4882a593Smuzhiyun #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 76*4882a593Smuzhiyun #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 77*4882a593Smuzhiyun #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 78*4882a593Smuzhiyun #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 79*4882a593Smuzhiyun #define I2C_START_STOP 0x20 /* START / STOP */ 80*4882a593Smuzhiyun #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define I2C_TIMEOUT_MS 10 /* 10 ms */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* _S3C24X0_I2C_H */ 85