1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * (C) Copyright 2008-2014 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <i2c.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/i2c.h>
18 #include <asm/arch/periph.h>
19 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /* i2c timerout */
25 #define I2C_TIMEOUT_MS 100
26 #define I2C_RETRY_COUNT 3
27
28 /* rk i2c fifo max transfer bytes */
29 #define RK_I2C_FIFO_SIZE 32
30
31 struct rk_i2c {
32 struct clk clk;
33 struct i2c_regs *regs;
34 unsigned int speed;
35 unsigned int cfg;
36 };
37
38 struct i2c_spec_values {
39 unsigned int min_low_ns;
40 unsigned int min_high_ns;
41 unsigned int max_rise_ns;
42 unsigned int max_fall_ns;
43 };
44
45 enum {
46 RK_I2C_VERSION0 = 0,
47 RK_I2C_VERSION1,
48 RK_I2C_VERSION5 = 5,
49 };
50
51 /********************* Private Variable Definition ***************************/
52
53 static const struct i2c_spec_values standard_mode_spec = {
54 .min_low_ns = 4700,
55 .min_high_ns = 4000,
56 .max_rise_ns = 1000,
57 .max_fall_ns = 300,
58 };
59
60 static const struct i2c_spec_values fast_mode_spec = {
61 .min_low_ns = 1300,
62 .min_high_ns = 600,
63 .max_rise_ns = 300,
64 .max_fall_ns = 300,
65 };
66
67 static const struct i2c_spec_values fast_modeplus_spec = {
68 .min_low_ns = 500,
69 .min_high_ns = 260,
70 .max_rise_ns = 120,
71 .max_fall_ns = 120,
72 };
73
rk_i2c_get_spec(unsigned int speed)74 static const struct i2c_spec_values *rk_i2c_get_spec(unsigned int speed)
75 {
76 if (speed == 1000)
77 return &fast_modeplus_spec;
78 else if (speed == 400)
79 return &fast_mode_spec;
80 else
81 return &standard_mode_spec;
82 }
83
rk_i2c_show_regs(struct i2c_regs * regs)84 static void rk_i2c_show_regs(struct i2c_regs *regs)
85 {
86 #ifdef DEBUG
87 uint i;
88
89 debug("i2c_con: 0x%08x\n", readl(®s->con));
90 debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv));
91 debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr));
92 debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr));
93 debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt));
94 debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt));
95 debug("i2c_ien: 0x%08x\n", readl(®s->ien));
96 debug("i2c_ipd: 0x%08x\n", readl(®s->ipd));
97 debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt));
98 for (i = 0; i < 8; i++)
99 debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i]));
100 for (i = 0; i < 8; i++)
101 debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i]));
102 #endif
103 }
104
rk_i2c_get_div(int div,int * divh,int * divl)105 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
106 {
107 *divl = div / 2;
108 if (div % 2 == 0)
109 *divh = div / 2;
110 else
111 *divh = DIV_ROUND_UP(div, 2);
112 }
113
114 /*
115 * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
116 * SCL = PCLK / SCLK Divisor
117 * i2c_rate = PCLK
118 */
rk_i2c_set_clk(struct rk_i2c * i2c,unsigned int scl_rate)119 static void rk_i2c_set_clk(struct rk_i2c *i2c, unsigned int scl_rate)
120 {
121 unsigned int i2c_rate;
122 int div, divl, divh;
123
124 /* First get i2c rate from pclk */
125 i2c_rate = clk_get_rate(&i2c->clk);
126
127 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
128 divh = 0;
129 divl = 0;
130 if (div >= 0)
131 rk_i2c_get_div(div, &divh, &divl);
132 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
133
134 debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
135 scl_rate);
136 debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
137 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
138 }
139
rk_i2c_adapter_clk(struct rk_i2c * i2c,unsigned int scl_rate)140 static int rk_i2c_adapter_clk(struct rk_i2c *i2c, unsigned int scl_rate)
141 {
142 const struct i2c_spec_values *spec;
143 unsigned int min_total_div, min_low_div, min_high_div, min_hold_div;
144 unsigned int low_div, high_div, extra_div, extra_low_div;
145 unsigned int min_low_ns, min_high_ns;
146 unsigned int start_setup = 0;
147 unsigned int i2c_rate = clk_get_rate(&i2c->clk);
148 unsigned int speed;
149
150 debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
151 scl_rate);
152
153 if (scl_rate <= 100000 && scl_rate >= 1000) {
154 start_setup = 1;
155 speed = 100;
156 } else if (scl_rate <= 400000 && scl_rate >= 100000) {
157 speed = 400;
158 } else if (scl_rate <= 1000000 && scl_rate > 400000) {
159 speed = 1000;
160 } else {
161 debug("invalid i2c speed : %d\n", scl_rate);
162 return -EINVAL;
163 }
164
165 spec = rk_i2c_get_spec(speed);
166 i2c_rate = DIV_ROUND_UP(i2c_rate, 1000);
167 speed = DIV_ROUND_UP(scl_rate, 1000);
168
169 min_total_div = DIV_ROUND_UP(i2c_rate, speed * 8);
170
171 min_high_ns = spec->max_rise_ns + spec->min_high_ns;
172 min_high_div = DIV_ROUND_UP(i2c_rate * min_high_ns, 8 * 1000000);
173
174 min_low_ns = spec->max_fall_ns + spec->min_low_ns;
175 min_low_div = DIV_ROUND_UP(i2c_rate * min_low_ns, 8 * 1000000);
176
177 min_high_div = (min_high_div < 1) ? 2 : min_high_div;
178 min_low_div = (min_low_div < 1) ? 2 : min_low_div;
179
180 min_hold_div = min_high_div + min_low_div;
181
182 if (min_hold_div >= min_total_div) {
183 high_div = min_high_div;
184 low_div = min_low_div;
185 } else {
186 extra_div = min_total_div - min_hold_div;
187 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
188 min_hold_div);
189
190 low_div = min_low_div + extra_low_div;
191 high_div = min_high_div + (extra_div - extra_low_div);
192 }
193
194 high_div--;
195 low_div--;
196
197 if (high_div > 0xffff || low_div > 0xffff)
198 return -EINVAL;
199
200 /* 1 for data hold/setup time is enough */
201 i2c->cfg = I2C_CON_SDA_CFG(1) | I2C_CON_STA_CFG(start_setup);
202 writel((high_div << I2C_CLK_DIV_HIGH_SHIFT) | low_div,
203 &i2c->regs->clkdiv);
204
205 debug("set clk(I2C_TIMING: 0x%08x)\n", i2c->cfg);
206 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
207
208 return 0;
209 }
210
rk_i2c_send_start_bit(struct rk_i2c * i2c,u32 con)211 static int rk_i2c_send_start_bit(struct rk_i2c *i2c, u32 con)
212 {
213 struct i2c_regs *regs = i2c->regs;
214 ulong start;
215
216 debug("I2c Send Start bit.\n");
217 writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
218
219 writel(I2C_STARTIEN, ®s->ien);
220 writel(I2C_CON_EN | I2C_CON_START | i2c->cfg | con, ®s->con);
221
222 start = get_timer(0);
223 while (1) {
224 if (readl(®s->ipd) & I2C_STARTIPD) {
225 writel(I2C_STARTIPD, ®s->ipd);
226 break;
227 }
228 if (get_timer(start) > I2C_TIMEOUT_MS) {
229 debug("I2C Send Start Bit Timeout\n");
230 rk_i2c_show_regs(regs);
231 return -ETIMEDOUT;
232 }
233 udelay(1);
234 }
235
236 /* clean start bit */
237 writel(I2C_CON_EN | i2c->cfg | con, ®s->con);
238
239 return 0;
240 }
241
rk_i2c_send_stop_bit(struct rk_i2c * i2c)242 static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
243 {
244 struct i2c_regs *regs = i2c->regs;
245 ulong start;
246
247 debug("I2c Send Stop bit.\n");
248 writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
249
250 writel(I2C_CON_EN | i2c->cfg | I2C_CON_STOP, ®s->con);
251 writel(I2C_CON_STOP, ®s->ien);
252
253 start = get_timer(0);
254 while (1) {
255 if (readl(®s->ipd) & I2C_STOPIPD) {
256 writel(I2C_STOPIPD, ®s->ipd);
257 break;
258 }
259 if (get_timer(start) > I2C_TIMEOUT_MS) {
260 debug("I2C Send Start Bit Timeout\n");
261 rk_i2c_show_regs(regs);
262 return -ETIMEDOUT;
263 }
264 udelay(1);
265 }
266
267 udelay(1);
268 return 0;
269 }
270
rk_i2c_disable(struct rk_i2c * i2c)271 static inline void rk_i2c_disable(struct rk_i2c *i2c)
272 {
273 writel(0, &i2c->regs->ien);
274 writel(I2C_IPD_ALL_CLEAN, &i2c->regs->ipd);
275 writel(0, &i2c->regs->con);
276 }
277
rk_i2c_read(struct rk_i2c * i2c,uchar chip,uint reg,uint r_len,uchar * buf,uint b_len,bool snd)278 static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
279 uchar *buf, uint b_len, bool snd)
280 {
281 struct i2c_regs *regs = i2c->regs;
282 uchar *pbuf = buf;
283 uint bytes_remain_len = b_len;
284 uint bytes_xferred = 0;
285 uint words_xferred = 0;
286 ulong start;
287 uint con = 0;
288 uint rxdata;
289 uint i, j;
290 int err = 0;
291 bool snd_chunk = false;
292
293 debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
294 chip, reg, r_len, b_len);
295
296 /* If the second message for TRX read, resetting internal state. */
297 if (snd)
298 writel(0, ®s->con);
299
300 writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr);
301 if (r_len == 0) {
302 writel(0, ®s->mrxraddr);
303 } else if (r_len < 4) {
304 writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr);
305 } else {
306 debug("I2C Read: addr len %d not supported\n", r_len);
307 return -EIO;
308 }
309
310 while (bytes_remain_len) {
311 if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
312 con = I2C_CON_EN;
313 bytes_xferred = 32;
314 } else {
315 /*
316 * The hw can read up to 32 bytes at a time. If we need
317 * more than one chunk, send an ACK after the last byte.
318 */
319 con = I2C_CON_EN | I2C_CON_LASTACK;
320 bytes_xferred = bytes_remain_len;
321 }
322 words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
323
324 /*
325 * make sure we are in plain RX mode if we read a second chunk;
326 * and first rx read need to send start bit.
327 */
328 if (snd_chunk) {
329 con |= I2C_CON_MOD(I2C_MODE_RX);
330 writel(con | i2c->cfg, ®s->con);
331 } else {
332 con |= I2C_CON_MOD(I2C_MODE_TRX);
333 err = rk_i2c_send_start_bit(i2c, con);
334 if (err)
335 return err;
336 }
337
338 writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien);
339 writel(bytes_xferred, ®s->mrxcnt);
340
341 start = get_timer(0);
342 while (1) {
343 if (readl(®s->ipd) & I2C_NAKRCVIPD) {
344 writel(I2C_NAKRCVIPD, ®s->ipd);
345 err = -EREMOTEIO;
346 goto i2c_exit;
347 }
348 if (readl(®s->ipd) & I2C_MBRFIPD) {
349 writel(I2C_MBRFIPD, ®s->ipd);
350 break;
351 }
352 if (get_timer(start) > I2C_TIMEOUT_MS) {
353 debug("I2C Read Data Timeout\n");
354 err = -ETIMEDOUT;
355 rk_i2c_show_regs(regs);
356 goto i2c_exit;
357 }
358 udelay(1);
359 }
360
361 for (i = 0; i < words_xferred; i++) {
362 rxdata = readl(®s->rxdata[i]);
363 debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
364 for (j = 0; j < 4; j++) {
365 if ((i * 4 + j) == bytes_xferred)
366 break;
367 *pbuf++ = (rxdata >> (j * 8)) & 0xff;
368 }
369 }
370
371 bytes_remain_len -= bytes_xferred;
372 snd_chunk = true;
373 debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
374 }
375
376 i2c_exit:
377 return err;
378 }
379
rk_i2c_write(struct rk_i2c * i2c,uchar chip,uint reg,uint r_len,uchar * buf,uint b_len)380 static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
381 uchar *buf, uint b_len)
382 {
383 struct i2c_regs *regs = i2c->regs;
384 int err = 0;
385 uchar *pbuf = buf;
386 uint bytes_remain_len = b_len + r_len + 1;
387 uint bytes_xferred = 0;
388 uint words_xferred = 0;
389 bool next = false;
390 ulong start;
391 uint txdata;
392 uint i, j;
393
394 debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
395 chip, reg, r_len, b_len);
396
397 while (bytes_remain_len) {
398 if (bytes_remain_len > RK_I2C_FIFO_SIZE)
399 bytes_xferred = RK_I2C_FIFO_SIZE;
400 else
401 bytes_xferred = bytes_remain_len;
402 words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
403
404 for (i = 0; i < words_xferred; i++) {
405 txdata = 0;
406 for (j = 0; j < 4; j++) {
407 if ((i * 4 + j) == bytes_xferred)
408 break;
409
410 if (i == 0 && j == 0 && pbuf == buf) {
411 txdata |= (chip << 1);
412 } else if (i == 0 && j <= r_len && pbuf == buf) {
413 txdata |= (reg &
414 (0xff << ((j - 1) * 8))) << 8;
415 } else {
416 txdata |= (*pbuf++)<<(j * 8);
417 }
418 }
419 writel(txdata, ®s->txdata[i]);
420 debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
421 }
422
423 /* If the write is the first, need to send start bit */
424 if (!next) {
425 err = rk_i2c_send_start_bit(i2c, I2C_CON_EN |
426 I2C_CON_MOD(I2C_MODE_TX));
427 if (err)
428 return err;
429 next = true;
430 } else {
431 writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX) | i2c->cfg,
432 ®s->con);
433 }
434 writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien);
435 writel(bytes_xferred, ®s->mtxcnt);
436
437 start = get_timer(0);
438 while (1) {
439 if (readl(®s->ipd) & I2C_NAKRCVIPD) {
440 writel(I2C_NAKRCVIPD, ®s->ipd);
441 err = -EREMOTEIO;
442 goto i2c_exit;
443 }
444 if (readl(®s->ipd) & I2C_MBTFIPD) {
445 writel(I2C_MBTFIPD, ®s->ipd);
446 break;
447 }
448 if (get_timer(start) > I2C_TIMEOUT_MS) {
449 debug("I2C Write Data Timeout\n");
450 err = -ETIMEDOUT;
451 rk_i2c_show_regs(regs);
452 goto i2c_exit;
453 }
454 udelay(1);
455 }
456
457 bytes_remain_len -= bytes_xferred;
458 debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
459 }
460
461 i2c_exit:
462 return err;
463 }
464
rockchip_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)465 static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
466 int nmsgs)
467 {
468 struct rk_i2c *i2c = dev_get_priv(bus);
469 bool snd = false; /* second message for TRX read */
470 int ret;
471 #ifdef CONFIG_IRQ
472 ulong flags;
473 #endif
474
475 debug("i2c_xfer: %d messages\n", nmsgs);
476 if (nmsgs > 2 || ((nmsgs == 2) && (msg->flags & I2C_M_RD))) {
477 debug("Not support more messages now, split them\n");
478 return -EINVAL;
479 }
480
481 #ifdef CONFIG_IRQ
482 local_irq_save(flags);
483 #endif
484 /* Nack enabled */
485 i2c->cfg |= I2C_CON_ACTACK;
486 for (; nmsgs > 0; nmsgs--, msg++) {
487 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
488
489 if (msg->flags & I2C_M_RD) {
490 /* If snd is true, it is TRX mode. */
491 ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
492 msg->len, snd);
493 } else {
494 snd = true;
495 ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
496 msg->len);
497 }
498
499 if (ret) {
500 debug("i2c_write: error sending\n");
501 goto exit;
502 }
503 }
504
505 exit:
506 rk_i2c_send_stop_bit(i2c);
507 rk_i2c_disable(i2c);
508 #ifdef CONFIG_IRQ
509 local_irq_restore(flags);
510 #endif
511 return ret;
512 }
513
rk3x_i2c_get_version(struct rk_i2c * i2c)514 static unsigned int rk3x_i2c_get_version(struct rk_i2c *i2c)
515 {
516 struct i2c_regs *regs = i2c->regs;
517 uint version;
518
519 version = readl(®s->con) & I2C_CON_VERSION;
520
521 return version >>= I2C_CON_VERSION_SHIFT;
522 }
523
rockchip_i2c_set_bus_speed(struct udevice * bus,unsigned int speed)524 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
525 {
526 struct rk_i2c *i2c = dev_get_priv(bus);
527
528 if (rk3x_i2c_get_version(i2c) >= RK_I2C_VERSION1)
529 rk_i2c_adapter_clk(i2c, speed);
530 else
531 rk_i2c_set_clk(i2c, speed);
532
533 return 0;
534 }
535
rockchip_i2c_ofdata_to_platdata(struct udevice * bus)536 static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
537 {
538 struct rk_i2c *priv = dev_get_priv(bus);
539 int ret;
540
541 ret = clk_get_by_index(bus, 0, &priv->clk);
542 if (ret < 0) {
543 debug("%s: Could not get clock for %s: %d\n", __func__,
544 bus->name, ret);
545 return ret;
546 }
547
548 return 0;
549 }
550
rockchip_i2c_probe(struct udevice * bus)551 static int rockchip_i2c_probe(struct udevice *bus)
552 {
553 struct rk_i2c *priv = dev_get_priv(bus);
554
555 priv->regs = dev_read_addr_ptr(bus);
556
557 return 0;
558 }
559
560 static const struct dm_i2c_ops rockchip_i2c_ops = {
561 .xfer = rockchip_i2c_xfer,
562 .set_bus_speed = rockchip_i2c_set_bus_speed,
563 };
564
565 static const struct udevice_id rockchip_i2c_ids[] = {
566 { .compatible = "rockchip,rk3066-i2c" },
567 { .compatible = "rockchip,rk3188-i2c" },
568 { .compatible = "rockchip,rk3288-i2c" },
569 { .compatible = "rockchip,rk3328-i2c" },
570 { .compatible = "rockchip,rk3399-i2c" },
571 { .compatible = "rockchip,rk3228-i2c" },
572 { .compatible = "rockchip,rv1108-i2c" },
573 { }
574 };
575
576 U_BOOT_DRIVER(i2c_rockchip) = {
577 .name = "i2c_rockchip",
578 .id = UCLASS_I2C,
579 .of_match = rockchip_i2c_ids,
580 .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
581 .probe = rockchip_i2c_probe,
582 .priv_auto_alloc_size = sizeof(struct rk_i2c),
583 .ops = &rockchip_i2c_ops,
584 };
585