1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Marvell Inc, <www.marvell.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MV_I2C_H_ 9*4882a593Smuzhiyun #define _MV_I2C_H_ 10*4882a593Smuzhiyun extern void i2c_clk_enable(void); 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Shall the current transfer have a start/stop condition? */ 13*4882a593Smuzhiyun #define I2C_COND_NORMAL 0 14*4882a593Smuzhiyun #define I2C_COND_START 1 15*4882a593Smuzhiyun #define I2C_COND_STOP 2 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Shall the current transfer be ack/nacked or being waited for it? */ 18*4882a593Smuzhiyun #define I2C_ACKNAK_WAITACK 1 19*4882a593Smuzhiyun #define I2C_ACKNAK_SENDACK 2 20*4882a593Smuzhiyun #define I2C_ACKNAK_SENDNAK 4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Specify who shall transfer the data (master or slave) */ 23*4882a593Smuzhiyun #define I2C_READ 0 24*4882a593Smuzhiyun #define I2C_WRITE 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define I2C_ISR_INIT 0x7FF 29*4882a593Smuzhiyun /* ----- Control register bits ---------------------------------------- */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define ICR_START 0x1 /* start bit */ 32*4882a593Smuzhiyun #define ICR_STOP 0x2 /* stop bit */ 33*4882a593Smuzhiyun #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ 34*4882a593Smuzhiyun #define ICR_TB 0x8 /* transfer byte bit */ 35*4882a593Smuzhiyun #define ICR_MA 0x10 /* master abort */ 36*4882a593Smuzhiyun #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ 37*4882a593Smuzhiyun #define ICR_IUE 0x40 /* unit enable */ 38*4882a593Smuzhiyun #define ICR_GCD 0x80 /* general call disable */ 39*4882a593Smuzhiyun #define ICR_ITEIE 0x100 /* enable tx interrupts */ 40*4882a593Smuzhiyun #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ 41*4882a593Smuzhiyun #define ICR_BEIE 0x400 /* enable bus error ints */ 42*4882a593Smuzhiyun #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ 43*4882a593Smuzhiyun #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ 44*4882a593Smuzhiyun #define ICR_SADIE 0x2000 /* slave address detected int enable */ 45*4882a593Smuzhiyun #define ICR_UR 0x4000 /* unit reset */ 46*4882a593Smuzhiyun #ifdef CONFIG_ARMADA_3700 47*4882a593Smuzhiyun #define ICR_SM 0x00000 /* Standard Mode */ 48*4882a593Smuzhiyun #define ICR_FM 0x10000 /* Fast Mode */ 49*4882a593Smuzhiyun #define ICR_MODE_MASK 0x30000 /* Mode mask */ 50*4882a593Smuzhiyun #else 51*4882a593Smuzhiyun #define ICR_SM 0x00000 /* Standard Mode */ 52*4882a593Smuzhiyun #define ICR_FM 0x08000 /* Fast Mode */ 53*4882a593Smuzhiyun #define ICR_MODE_MASK 0x18000 /* Mode mask */ 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* ----- Status register bits ----------------------------------------- */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define ISR_RWM 0x1 /* read/write mode */ 59*4882a593Smuzhiyun #define ISR_ACKNAK 0x2 /* ack/nak status */ 60*4882a593Smuzhiyun #define ISR_UB 0x4 /* unit busy */ 61*4882a593Smuzhiyun #define ISR_IBB 0x8 /* bus busy */ 62*4882a593Smuzhiyun #define ISR_SSD 0x10 /* slave stop detected */ 63*4882a593Smuzhiyun #define ISR_ALD 0x20 /* arbitration loss detected */ 64*4882a593Smuzhiyun #define ISR_ITE 0x40 /* tx buffer empty */ 65*4882a593Smuzhiyun #define ISR_IRF 0x80 /* rx buffer full */ 66*4882a593Smuzhiyun #define ISR_GCAD 0x100 /* general call address detected */ 67*4882a593Smuzhiyun #define ISR_SAD 0x200 /* slave address detected */ 68*4882a593Smuzhiyun #define ISR_BED 0x400 /* bus error no ACK/NAK */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71