1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 - 2016 Xilinx, Inc.
3*4882a593Smuzhiyun * Written by Michal Simek
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <i2c.h>
12*4882a593Smuzhiyun #include <asm/gpio.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum pca_type {
17*4882a593Smuzhiyun PCA9544,
18*4882a593Smuzhiyun PCA9547,
19*4882a593Smuzhiyun PCA9548
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct chip_desc {
23*4882a593Smuzhiyun u8 enable;
24*4882a593Smuzhiyun enum muxtype {
25*4882a593Smuzhiyun pca954x_ismux = 0,
26*4882a593Smuzhiyun pca954x_isswi,
27*4882a593Smuzhiyun } muxtype;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct pca954x_priv {
31*4882a593Smuzhiyun u32 addr; /* I2C mux address */
32*4882a593Smuzhiyun u32 width; /* I2C mux width - number of busses */
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct chip_desc chips[] = {
36*4882a593Smuzhiyun [PCA9544] = {
37*4882a593Smuzhiyun .enable = 0x4,
38*4882a593Smuzhiyun .muxtype = pca954x_ismux,
39*4882a593Smuzhiyun },
40*4882a593Smuzhiyun [PCA9547] = {
41*4882a593Smuzhiyun .enable = 0x8,
42*4882a593Smuzhiyun .muxtype = pca954x_ismux,
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun [PCA9548] = {
45*4882a593Smuzhiyun .enable = 0x8,
46*4882a593Smuzhiyun .muxtype = pca954x_isswi,
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
pca954x_deselect(struct udevice * mux,struct udevice * bus,uint channel)50*4882a593Smuzhiyun static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
51*4882a593Smuzhiyun uint channel)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct pca954x_priv *priv = dev_get_priv(mux);
54*4882a593Smuzhiyun uchar byte = 0;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return dm_i2c_write(mux, priv->addr, &byte, 1);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
pca954x_select(struct udevice * mux,struct udevice * bus,uint channel)59*4882a593Smuzhiyun static int pca954x_select(struct udevice *mux, struct udevice *bus,
60*4882a593Smuzhiyun uint channel)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct pca954x_priv *priv = dev_get_priv(mux);
63*4882a593Smuzhiyun const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];
64*4882a593Smuzhiyun uchar byte;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (chip->muxtype == pca954x_ismux)
67*4882a593Smuzhiyun byte = channel | chip->enable;
68*4882a593Smuzhiyun else
69*4882a593Smuzhiyun byte = 1 << channel;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return dm_i2c_write(mux, priv->addr, &byte, 1);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct i2c_mux_ops pca954x_ops = {
75*4882a593Smuzhiyun .select = pca954x_select,
76*4882a593Smuzhiyun .deselect = pca954x_deselect,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct udevice_id pca954x_ids[] = {
80*4882a593Smuzhiyun { .compatible = "nxp,pca9544", .data = PCA9544 },
81*4882a593Smuzhiyun { .compatible = "nxp,pca9547", .data = PCA9547 },
82*4882a593Smuzhiyun { .compatible = "nxp,pca9548", .data = PCA9548 },
83*4882a593Smuzhiyun { }
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
pca954x_ofdata_to_platdata(struct udevice * dev)86*4882a593Smuzhiyun static int pca954x_ofdata_to_platdata(struct udevice *dev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct pca954x_priv *priv = dev_get_priv(dev);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun priv->addr = dev_read_u32_default(dev, "reg", 0);
91*4882a593Smuzhiyun if (!priv->addr) {
92*4882a593Smuzhiyun debug("MUX not found\n");
93*4882a593Smuzhiyun return -ENODEV;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun priv->width = dev_get_driver_data(dev);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!priv->width) {
98*4882a593Smuzhiyun debug("No I2C MUX width specified\n");
99*4882a593Smuzhiyun return -EINVAL;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun debug("Device %s at 0x%x with width %d\n",
103*4882a593Smuzhiyun dev->name, priv->addr, priv->width);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun U_BOOT_DRIVER(pca954x) = {
109*4882a593Smuzhiyun .name = "pca954x",
110*4882a593Smuzhiyun .id = UCLASS_I2C_MUX,
111*4882a593Smuzhiyun .of_match = pca954x_ids,
112*4882a593Smuzhiyun .ops = &pca954x_ops,
113*4882a593Smuzhiyun .ofdata_to_platdata = pca954x_ofdata_to_platdata,
114*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct pca954x_priv),
115*4882a593Smuzhiyun };
116