1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <max96755f.h>
11*4882a593Smuzhiyun #include <dm/of_access.h>
12*4882a593Smuzhiyun #include <dm/ofnode.h>
13*4882a593Smuzhiyun
max96755f_select(struct udevice * mux,struct udevice * bus,uint channel)14*4882a593Smuzhiyun static int max96755f_select(struct udevice *mux, struct udevice *bus,
15*4882a593Smuzhiyun uint channel)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct max96755f_priv *priv = dev_get_priv(mux);
18*4882a593Smuzhiyun int link_cfg;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun dm_i2c_reg_clrset(priv->dev, 0x0001, DIS_REM_CC,
21*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 0));
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun if (!priv->split_mode)
24*4882a593Smuzhiyun return 0;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun link_cfg = dm_i2c_reg_read(priv->dev, 0x0010);
27*4882a593Smuzhiyun if ((link_cfg & LINK_CFG) == SPLITTER_MODE)
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (channel == 0 && (link_cfg & LINK_CFG) != LINKA) {
31*4882a593Smuzhiyun dm_i2c_reg_clrset(priv->dev, 0x0010,
32*4882a593Smuzhiyun RESET_ONESHOT | AUTO_LINK | LINK_CFG,
33*4882a593Smuzhiyun FIELD_PREP(RESET_ONESHOT, 1) |
34*4882a593Smuzhiyun FIELD_PREP(AUTO_LINK, 0) |
35*4882a593Smuzhiyun FIELD_PREP(LINK_CFG, LINKA));
36*4882a593Smuzhiyun mdelay(50);
37*4882a593Smuzhiyun } else if (channel == 1 && (link_cfg & LINK_CFG) != LINKB) {
38*4882a593Smuzhiyun dm_i2c_reg_clrset(priv->dev, 0x0010,
39*4882a593Smuzhiyun RESET_ONESHOT | AUTO_LINK | LINK_CFG,
40*4882a593Smuzhiyun FIELD_PREP(RESET_ONESHOT, 1) |
41*4882a593Smuzhiyun FIELD_PREP(AUTO_LINK, 0) |
42*4882a593Smuzhiyun FIELD_PREP(LINK_CFG, LINKB));
43*4882a593Smuzhiyun mdelay(50);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
max96755f_deselect(struct udevice * mux,struct udevice * bus,uint channel)49*4882a593Smuzhiyun static int max96755f_deselect(struct udevice *mux, struct udevice *bus,
50*4882a593Smuzhiyun uint channel)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct max96755f_priv *priv = dev_get_priv(mux);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun dm_i2c_reg_clrset(priv->dev, 0x0001, DIS_REM_CC,
55*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct i2c_mux_ops max96755f_ops = {
60*4882a593Smuzhiyun .select = max96755f_select,
61*4882a593Smuzhiyun .deselect = max96755f_deselect,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
max96755f_power_on(struct max96755f_priv * priv)64*4882a593Smuzhiyun static int max96755f_power_on(struct max96755f_priv *priv)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->enable_gpio)) {
69*4882a593Smuzhiyun dm_gpio_set_value(&priv->enable_gpio, 1);
70*4882a593Smuzhiyun mdelay(100);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun ret = dm_i2c_reg_clrset(priv->dev, 0x0010, RESET_ALL,
74*4882a593Smuzhiyun FIELD_PREP(RESET_ALL, 1));
75*4882a593Smuzhiyun if (ret < 0)
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun mdelay(100);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun dm_i2c_reg_clrset(priv->dev, 0x0001, DIS_REM_CC,
81*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
max96755f_probe(struct udevice * dev)85*4882a593Smuzhiyun static int max96755f_probe(struct udevice *dev)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct max96755f_priv *priv = dev_get_priv(dev);
88*4882a593Smuzhiyun ofnode child;
89*4882a593Smuzhiyun u8 nr = 0;
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, 2);
93*4882a593Smuzhiyun if (ret)
94*4882a593Smuzhiyun return ret;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun priv->dev = dev;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = gpio_request_by_name(dev, "enable-gpios", 0,
99*4882a593Smuzhiyun &priv->enable_gpio, GPIOD_IS_OUT);
100*4882a593Smuzhiyun if (ret && ret != -ENOENT) {
101*4882a593Smuzhiyun dev_err(dev, "%s: failed to get enable GPIO: %d\n", __func__, ret);
102*4882a593Smuzhiyun return ret;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = max96755f_power_on(priv);
106*4882a593Smuzhiyun if (ret) {
107*4882a593Smuzhiyun dev_err(dev, "%s: failed to power on: %d\n", __func__, ret);
108*4882a593Smuzhiyun return ret;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ofnode_for_each_subnode(child, dev_ofnode(dev)) {
112*4882a593Smuzhiyun if (!ofnode_is_available(child) ||
113*4882a593Smuzhiyun !of_find_property(ofnode_to_np(child), "reg", NULL))
114*4882a593Smuzhiyun continue;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun nr++;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (nr == 2)
120*4882a593Smuzhiyun priv->split_mode = true;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static const struct udevice_id max96755f_of_match[] = {
126*4882a593Smuzhiyun { .compatible = "maxim,max96755f" },
127*4882a593Smuzhiyun {}
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun U_BOOT_DRIVER(max96755f) = {
131*4882a593Smuzhiyun .name = "max96755f",
132*4882a593Smuzhiyun .id = UCLASS_I2C_MUX,
133*4882a593Smuzhiyun .of_match = max96755f_of_match,
134*4882a593Smuzhiyun .bind = dm_scan_fdt_dev,
135*4882a593Smuzhiyun .probe = max96755f_probe,
136*4882a593Smuzhiyun .ops = &max96755f_ops,
137*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct max96755f_priv),
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140