1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <asm-generic/gpio.h>
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <i2c.h>
11*4882a593Smuzhiyun #include <max96745.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct max96745_priv {
14*4882a593Smuzhiyun struct udevice *dev;
15*4882a593Smuzhiyun struct gpio_desc enable_gpio;
16*4882a593Smuzhiyun struct gpio_desc pwdnb_gpio;
17*4882a593Smuzhiyun bool idle_disc;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
max96745_select(struct udevice * mux,struct udevice * bus,uint channel)20*4882a593Smuzhiyun static int max96745_select(struct udevice *mux, struct udevice *bus,
21*4882a593Smuzhiyun uint channel)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct max96745_priv *priv = dev_get_priv(mux);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun if (!priv->idle_disc)
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (channel == 1)
29*4882a593Smuzhiyun dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
30*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 0));
31*4882a593Smuzhiyun else
32*4882a593Smuzhiyun dm_i2c_reg_clrset(mux, 0x0076, DIS_REM_CC,
33*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 0));
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
max96745_deselect(struct udevice * mux,struct udevice * bus,uint channel)38*4882a593Smuzhiyun static int max96745_deselect(struct udevice *mux, struct udevice *bus,
39*4882a593Smuzhiyun uint channel)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct max96745_priv *priv = dev_get_priv(mux);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (!priv->idle_disc)
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (channel == 1)
47*4882a593Smuzhiyun dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
48*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
49*4882a593Smuzhiyun else
50*4882a593Smuzhiyun dm_i2c_reg_clrset(mux, 0x0076, DIS_REM_CC,
51*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static const struct i2c_mux_ops max96745_ops = {
57*4882a593Smuzhiyun .select = max96745_select,
58*4882a593Smuzhiyun .deselect = max96745_deselect,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
max96745_power_on(struct max96745_priv * priv)61*4882a593Smuzhiyun static int max96745_power_on(struct max96745_priv *priv)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->enable_gpio)) {
66*4882a593Smuzhiyun dm_gpio_set_value(&priv->enable_gpio, 1);
67*4882a593Smuzhiyun mdelay(200);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (dm_gpio_is_valid(&priv->pwdnb_gpio)) {
71*4882a593Smuzhiyun dm_gpio_set_value(&priv->pwdnb_gpio, 0);
72*4882a593Smuzhiyun mdelay(30);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Set for I2C Fast-mode speed */
76*4882a593Smuzhiyun ret = dm_i2c_reg_write(priv->dev, 0x0070, 0x16);
77*4882a593Smuzhiyun if (ret < 0)
78*4882a593Smuzhiyun return ret;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (priv->idle_disc) {
81*4882a593Smuzhiyun ret = dm_i2c_reg_clrset(priv->dev, 0x0076, DIS_REM_CC,
82*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
83*4882a593Smuzhiyun if (ret < 0)
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun ret = dm_i2c_reg_clrset(priv->dev, 0x0086, DIS_REM_CC,
87*4882a593Smuzhiyun FIELD_PREP(DIS_REM_CC, 1));
88*4882a593Smuzhiyun if (ret < 0)
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
max96745_probe(struct udevice * dev)95*4882a593Smuzhiyun static int max96745_probe(struct udevice *dev)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct max96745_priv *priv = dev_get_priv(dev);
98*4882a593Smuzhiyun int ret;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, 2);
101*4882a593Smuzhiyun if (ret)
102*4882a593Smuzhiyun return ret;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun priv->dev = dev;
105*4882a593Smuzhiyun priv->idle_disc = dev_read_bool(dev, "i2c-mux-idle-disconnect");
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ret = gpio_request_by_name(dev, "enable-gpios", 0,
108*4882a593Smuzhiyun &priv->enable_gpio, GPIOD_IS_OUT);
109*4882a593Smuzhiyun if (ret && ret != -ENOENT) {
110*4882a593Smuzhiyun dev_err(dev, "%s: failed to get enable GPIO: %d\n", __func__, ret);
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun ret = gpio_request_by_name(dev, "pwdnb-gpios", 0,
115*4882a593Smuzhiyun &priv->pwdnb_gpio, GPIOD_IS_OUT);
116*4882a593Smuzhiyun if (ret && ret != -ENOENT) {
117*4882a593Smuzhiyun dev_err(dev, "%s: failed to get pwdnb GPIO: %d\n", __func__, ret);
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun max96745_power_on(priv);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct udevice_id max96745_of_match[] = {
127*4882a593Smuzhiyun { .compatible = "maxim,max96745" },
128*4882a593Smuzhiyun {}
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun U_BOOT_DRIVER(max96745) = {
132*4882a593Smuzhiyun .name = "max96745",
133*4882a593Smuzhiyun .id = UCLASS_I2C_MUX,
134*4882a593Smuzhiyun .of_match = max96745_of_match,
135*4882a593Smuzhiyun .bind = dm_scan_fdt_dev,
136*4882a593Smuzhiyun .probe = max96745_probe,
137*4882a593Smuzhiyun .ops = &max96745_ops,
138*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct max96745_priv),
139*4882a593Smuzhiyun };
140